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Pepijn de Vos edited this page Nov 17, 2024 · 2 revisions

The VCC primitive is a logic high level generator, generating an output referred to as V. The VCC output is represented by the port name "V". This output can be used in digital circuit design as a reference point for high-level signals.

This device is supported in Apicula.

Ports

Port Size Direction
V 1 output

Verilog Instantiation

VCC vcc_inst (
    .V(V)
);
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