IBUF

The IBUF (Input Buffer) primitive, also referred to as the Input/Output Buffer, is a type of buffer used in Xilinx FPGAs. It provides input data to an output signal, with port descriptions including "I" for input data input signal and "O" for data output signal. The IBUF can be instantiated in Verilog using a specific syntax, although it is not explicitly stated in the provided text.

This device is supported in Apicula.

Ports

Port	Size	Direction
I	1	input
O	1	output

Verilog Instantiation

IBUF ibuf_inst (
    .I(I),
    .O(O)
);