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Pepijn de Vos edited this page Nov 19, 2024 · 4 revisions

DFF

The D Flip-Flop (DFF) primitive, pos-edge triggered, is commonly used for signal sampling and processing. The port diagram shows inputs D, CLK, and output QDFF. Port descriptions indicate that D is an input data input, CLK is an input clock input, and Q is an output data output.

This device is supported in Apicula.

Ports

Port Size Direction
CLK 1 input
D 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFF #(
    .INIT(INIT)
) dff_inst (
    .CLK(CLK),
    .D(D),
    .Q(Q)
);

DFFC

The Gowin DFFC (D Flip-Flop with asynchronous clear) primitive is a pos-edge triggered flip-flop, meaning that it captures the input data on the rising edge of the clock signal. The primitive has three ports: D for input data, CLK for clock input, and CLEAR for asynchronous clear, which is active-high. When CLEAR is high, the output Q is cleared to its initial value, which is 0 by default.

This device is supported in Apicula.

Ports

Port Size Direction
CLEAR 1 input
CLK 1 input
D 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFFC #(
    .INIT(INIT)
) dffc_inst (
    .CLEAR(CLEAR),
    .CLK(CLK),
    .D(D),
    .Q(Q)
);

DFFCE

The Gowin DFFCE primitive is a D flip-flop with clock enable and asynchronous clear. It is triggered by the rising edge, meaning it captures data on the rising edge of the clock input signal. The primitive has four inputs: D (data), CLK (clock), CLEAR (asynchronous clear), and CE (clock enable). When the CLEAR input is high, the output QDFFCE is asynchronously cleared to a logic 0. The primitive also has an optional parameter INIT that specifies the initial value of the flip-flop when powered on, which can be set to either '0' or '1'.

This device is supported in Apicula.

Ports

Port Size Direction
CE 1 input
CLEAR 1 input
CLK 1 input
D 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFFCE #(
    .INIT(INIT)
) dffce_inst (
    .CE(CE),
    .CLEAR(CLEAR),
    .CLK(CLK),
    .D(D),
    .Q(Q)
);

DFFE

The DFFE (D Flip-Flop with clock enable) primitive is a pos-edge triggered device that accepts data input "D" and enables its clocking based on signal "CE". The output "Q" provides the last valid value of "D" when "CE" is asserted. It has an initial value of 0, as specified by the parameter "INIT".

This device is supported in Apicula.

Ports

Port Size Direction
CE 1 input
CLK 1 input
D 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFFE #(
    .INIT(INIT)
) dffe_inst (
    .CE(CE),
    .CLK(CLK),
    .D(D),
    .Q(Q)
);

DFFN

The DFFN primitive is a generic D Flip-Flop with neg-edge clock, where data (D) is captured on the falling edge of the clock (CLK). The output (Q) will be the same as the input (D) at the next clock cycle. The initial value of the flip-flop is pre-set to '0' by default.

This device is supported in Apicula.

Ports

Port Size Direction
CLK 1 input
D 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFFN #(
    .INIT(INIT)
) dffn_inst (
    .CLK(CLK),
    .D(D),
    .Q(Q)
);

DFFNC

The DFFNC primitive is a neg-edge triggered D Flip-Flop with asynchronous clear. It has four ports: D (input data), CLK (clock input), CLEAR (asynchronous clear, active-high), and Q (output data). The default initial value of the DFFNC is 1'b0.

This device is supported in Apicula

Ports

Port Size Direction
CLEAR 1 input
CLK 1 input
D 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFFNC #(
    .INIT(INIT)
) dffnc_inst (
    .CLEAR(CLEAR),
    .CLK(CLK),
    .D(D),
    .Q(Q)
);

DFFNCE

The DFFNCE primitive is a D Flip-Flop with clock enable and asynchronous clear. It has three ports: Q (output), D (input data), CLK (clock input), CLEAR (asynchronous clear), and CE (clock enable). The flip-flop is neg-edge triggered, meaning it captures the input value on the falling edge of the clock signal when the clock enable (CE) is high.

This device is supported in Apicula

Ports

Port Size Direction
CE 1 input
CLEAR 1 input
CLK 1 input
D 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFFNCE #(
    .INIT(INIT)
) dffnce_inst (
    .CE(CE),
    .CLEAR(CLEAR),
    .CLK(CLK),
    .D(D),
    .Q(Q)
);

DFFNE

The Gowin DFFNE (D Flip-Flop with clock enable) primitive is a neg-edge triggered flip-flop. It has four ports: D (input), Q (output), CLK (clock input), and CE (clock enable input). The CE port is not mentioned in the summary, but according to the provided text, the functionality of this primitive includes a "CE" (clock enable) port.

This device is supported in Apicula.

Ports

Port Size Direction
CE 1 input
CLK 1 input
D 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFFNE #(
    .INIT(INIT)
) dffne_inst (
    .CE(CE),
    .CLK(CLK),
    .D(D),
    .Q(Q)
);

DFFNP

The DFFNP primitive is a digital flip-flop with asynchronous preset, which means that it can be preset (i.e., cleared) by an active-low asynchronous input. The functionality of this primitive is summarized as follows: the Q output will follow the D input when the CLK input is high, and the Q output will be set to 0 (reset) when the RESET input is low, regardless of the state of the other inputs.

This device is supported in Apicula

Ports

Port Size Direction
CLK 1 input
D 1 input
PRESET 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DFFNP #(
    .INIT(INIT)
) dffnp_inst (
    .CLK(CLK),
    .D(D),
    .PRESET(PRESET),
    .Q(Q)
);

DFFNPE

The DFFNPE primitive, also known as a D Flip-Flop with clock enable and asynchronous preset, is neg-edge triggered. It has four ports: D (data input), CLK (clock input), PRESET (asynchronous preset input), CE (clock enable input), and Q (output data). The primitive can be configured to have an initial value of either 1'b0 or 1'b1.

This device is supported in Apicula

Ports

Port Size Direction
CE 1 input
CLK 1 input
D 1 input
PRESET 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DFFNPE #(
    .INIT(INIT)
) dffnpe_inst (
    .CE(CE),
    .CLK(CLK),
    .D(D),
    .PRESET(PRESET),
    .Q(Q)
);

DFFNR

The DFFNR primitive is a generic flip-flop with synchronous reset, which is neg-edge triggered. It has four ports: D (data input), CLK (clock input), RESET (synchronous reset active-high), and Q (data output). The initial value of the data output is '0' by default.

This device is supported in Apicula.

Ports

Port Size Direction
CLK 1 input
D 1 input
Q 1 output
RESET 1 input

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFFNR #(
    .INIT(INIT)
) dffnr_inst (
    .CLK(CLK),
    .D(D),
    .Q(Q),
    .RESET(RESET)
);

DFFNRE

The DFFNRE (D Flip-Flop with clock enable and synchronous reset) primitive is a neg-edge triggered flip-flop, meaning that it captures the input data (D) on the falling edge of the clock signal. The "N" in its name indicates this characteristic. It has four ports: D for data input, CLK for clock input, RESET for synchronous reset (active-high), and CE for clock enable. When enabled by CE, the flip-flop can be clocked to update its output Q with the current value of D on each falling edge of CLK. If RESET is asserted high, it will immediately set Q to its initial value, which is 0 by default.

This device is supported in Apicula

Ports

Port Size Direction
CE 1 input
CLK 1 input
D 1 input
Q 1 output
RESET 1 input

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFFNRE #(
    .INIT(INIT)
) dffnre_inst (
    .CE(CE),
    .CLK(CLK),
    .D(D),
    .Q(Q),
    .RESET(RESET)
);

DFFNS

The DFFNS primitive is a digital flip-flop that captures the input data (D) on the falling edge of the clock signal (CLK), storing it in the output register Q. The SET input, active-high, has the effect of setting the output to 1 when asserted, regardless of the current state of the flip-flop.

This device is supported in Apicula

Ports

Port Size Direction
CLK 1 input
D 1 input
Q 1 output
SET 1 input

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DFFNS #(
    .INIT(INIT)
) dffns_inst (
    .CLK(CLK),
    .D(D),
    .Q(Q),
    .SET(SET)
);

DFFNSE

The DFFNSE primitive is a neg-edge triggered D Flip-Flop with clock enable and synchronous set. It has four ports: Q (output), D (input), CLK (clock input), SET (set input), and CE (clock enable input). The functionality of this primitive can be summarized as follows: the data from the D port is loaded into the flip-flop on the neg-edge of the clock signal when the clock enable input CE is high, and the set input SET can also load a new value into the flip-flop synchronously.

This device is supported in Apicula

Ports

Port Size Direction
CE 1 input
CLK 1 input
D 1 input
Q 1 output
SET 1 input

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DFFNSE #(
    .INIT(INIT)
) dffnse_inst (
    .CE(CE),
    .CLK(CLK),
    .D(D),
    .Q(Q),
    .SET(SET)
);

DFFP

The Gowin DFFP primitive is a D Flip-Flop with asynchronous preset, which is pos-edge triggered. It has four ports: "D" for data input, "CLK" for clock input, "PRESET" for asynchronous preset (active-high), and "Q" for data output. The default initial value of the primitive is 1'b1.

This device is supported in Apicula.

Ports

Port Size Direction
CLK 1 input
D 1 input
PRESET 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DFFP #(
    .INIT(INIT)
) dffp_inst (
    .CLK(CLK),
    .D(D),
    .PRESET(PRESET),
    .Q(Q)
);

DFFPE

The Gowin DFFPE primitive is a D flip-flop with clock enable and asynchronous preset, which is pos-edge triggered. It has ports for data input (D), clock input (CLK), asynchronous preset (PRESET), and clock enable (CE). The primitive is designed to update the output (Q) based on the rising edge of the CLK signal when CE is high, and can be preset to a specific value using the PRESET input.

This device is supported in Apicula.

Ports

Port Size Direction
CE 1 input
CLK 1 input
D 1 input
PRESET 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DFFPE #(
    .INIT(INIT)
) dffpe_inst (
    .CE(CE),
    .CLK(CLK),
    .D(D),
    .PRESET(PRESET),
    .Q(Q)
);

DFFR

The Gowin DFFR primitive is a D flip-flop with synchronous reset. It has four ports: D (data input), CLK (clock), Q (output), and RESET, but the functionality of the RESET port is not specified in the provided text. The primitive is pos-edge triggered, meaning that it updates its output on the rising edge of the clock signal.

This device is supported in Apicula.

Ports

Port Size Direction
CLK 1 input
D 1 input
Q 1 output
RESET 1 input

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFFR #(
    .INIT(INIT)
) dffr_inst (
    .CLK(CLK),
    .D(D),
    .Q(Q),
    .RESET(RESET)
);

DFFRE

The DFFRE primitive, also known as a D Flip-Flop with Clock Enable and Synchronous Reset, is a digital logic primitive that captures the input data on the rising edge of the clock (pos-edge triggered) when the clock enable signal is active. The synchronous reset signal can be used to reset the output to its initial value when high.

This device is supported in Apicula.

Ports

Port Size Direction
CE 1 input
CLK 1 input
D 1 input
Q 1 output
RESET 1 input

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DFFRE #(
    .INIT(INIT)
) dffre_inst (
    .CE(CE),
    .CLK(CLK),
    .D(D),
    .Q(Q),
    .RESET(RESET)
);

DFFS

The DFFS primitive is a D Flip-Flop with synchronous set, which is pos-edge triggered. It has three ports: D for input data, CLK for clock input, and SET for synchronous set, active-high.

This device is supported in Apicula.

Ports

Port Size Direction
CLK 1 input
D 1 input
Q 1 output
SET 1 input

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DFFS #(
    .INIT(INIT)
) dffs_inst (
    .CLK(CLK),
    .D(D),
    .Q(Q),
    .SET(SET)
);

DFFSE

The Gowin DFFSE primitive is a D flip-flop with clock enable and synchronous set, triggered by the rising edge. It has five ports: D (data input), CLK (clock input), SET (synchronous set signal), CE (clock enable signal), and Q (output data output). The parameters include INIT, which sets the initial value of the DFFSE to 1'b1. This primitive can be instantiated in a Verilog description using the following syntax: DFFSE instName (.D(D), .CLK(CLK), .SET(SET), .CE(CE), .Q(Q));. The SET signal is active-high, meaning it must be asserted high to set the output Q to 1.

This device is supported in Apicula.

Ports

Port Size Direction
CE 1 input
CLK 1 input
D 1 input
Q 1 output
SET 1 input

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DFFSE #(
    .INIT(INIT)
) dffse_inst (
    .CE(CE),
    .CLK(CLK),
    .D(D),
    .Q(Q),
    .SET(SET)
);
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