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AE350_SOC
Pepijn de Vos edited this page Nov 17, 2024
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2 revisions
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| AHB_CE | 1 | input |
| AHB_CLK | 1 | input |
| APB2AHB_CE | 1 | input |
| APB_CE | 8 | input |
| APB_CLK | 1 | input |
| APB_PADDR | 32 | output |
| APB_PENABLE | 1 | output |
| APB_PPROT | 3 | output |
| APB_PRDATA | 32 | input |
| APB_PREADY | 1 | input |
| APB_PSEL | 1 | output |
| APB_PSLVERR | 1 | input |
| APB_PSTRB | 4 | output |
| APB_PWDATA | 32 | output |
| APB_PWRITE | 1 | output |
| AXI_CE | 1 | input |
| CH0_PWM | 1 | output |
| CH0_PWMOE | 1 | output |
| CH1_PWM | 1 | output |
| CH1_PWMOE | 1 | output |
| CH2_PWM | 1 | output |
| CH2_PWMOE | 1 | output |
| CH3_PWM | 1 | output |
| CH3_PWMOE | 1 | output |
| CORE0_WFI_MODE | 1 | output |
| CORE_CE | 1 | input |
| CORE_CLK | 1 | input |
| DBG_TCK | 1 | input |
| DDR_CE | 1 | input |
| DDR_CLK | 1 | input |
| DDR_HADDR | 32 | output |
| DDR_HBURST | 3 | output |
| DDR_HPROT | 4 | output |
| DDR_HRDATA | 64 | input |
| DDR_HREADY | 1 | input |
| DDR_HRESP | 1 | input |
| DDR_HSIZE | 3 | output |
| DDR_HTRANS | 2 | output |
| DDR_HWDATA | 64 | output |
| DDR_HWRITE | 1 | output |
| DDR_RSTN | 1 | output |
| DMA_ACK | 8 | output |
| DMA_REQ | 8 | input |
| EMA | 3 | input |
| EMAS | 1 | input |
| EMAW | 2 | input |
| EXTM_HADDR | 32 | input |
| EXTM_HBURST | 3 | input |
| EXTM_HPROT | 4 | input |
| EXTM_HRDATA | 64 | output |
| EXTM_HREADY | 1 | input |
| EXTM_HREADYOUT | 1 | output |
| EXTM_HRESP | 1 | output |
| EXTM_HSEL | 1 | input |
| EXTM_HSIZE | 3 | input |
| EXTM_HTRANS | 2 | input |
| EXTM_HWDATA | 64 | input |
| EXTM_HWRITE | 1 | input |
| EXTS_HADDR | 32 | output |
| EXTS_HBURST | 3 | output |
| EXTS_HPROT | 4 | output |
| EXTS_HRDATA | 32 | input |
| EXTS_HREADYIN | 1 | input |
| EXTS_HRESP | 1 | input |
| EXTS_HSEL | 1 | output |
| EXTS_HSIZE | 3 | output |
| EXTS_HTRANS | 2 | output |
| EXTS_HWDATA | 32 | output |
| EXTS_HWRITE | 1 | output |
| GPIO_IN | 32 | input |
| GPIO_OE | 32 | output |
| GPIO_OUT | 32 | output |
| GP_INT | 16 | input |
| HRESETN | 1 | output |
| HW_RSTN | 1 | input |
| I2C_SCL | 1 | output |
| I2C_SCL_IN | 1 | input |
| I2C_SDA | 1 | output |
| I2C_SDA_IN | 1 | input |
| INTEG_TCK | 1 | input |
| INTEG_TDI | 1 | input |
| INTEG_TDO | 1 | output |
| INTEG_TMS | 1 | input |
| INTEG_TRST | 1 | input |
| PGEN_CHAIN_I | 1 | input |
| POR_N | 1 | input |
| PRDYN_CHAIN_O | 1 | output |
| PRESETN | 1 | output |
| RET1N | 1 | input |
| RET2N | 1 | input |
| ROM_HADDR | 32 | output |
| ROM_HRDATA | 32 | input |
| ROM_HREADY | 1 | input |
| ROM_HRESP | 1 | input |
| ROM_HTRANS | 2 | output |
| ROM_HWRITE | 1 | output |
| RTC_CLK | 1 | input |
| RTC_WAKEUP | 1 | output |
| SCAN_EN | 1 | input |
| SCAN_IN | 20 | input |
| SCAN_OUT | 20 | output |
| SCAN_TEST | 1 | input |
| SPI2_CLK_IN | 1 | input |
| SPI2_CLK_OE | 1 | output |
| SPI2_CLK_OUT | 1 | output |
| SPI2_CSN_IN | 1 | input |
| SPI2_CSN_OE | 1 | output |
| SPI2_CSN_OUT | 1 | output |
| SPI2_HOLDN_IN | 1 | input |
| SPI2_HOLDN_OE | 1 | output |
| SPI2_HOLDN_OUT | 1 | output |
| SPI2_MISO_IN | 1 | input |
| SPI2_MISO_OE | 1 | output |
| SPI2_MISO_OUT | 1 | output |
| SPI2_MOSI_IN | 1 | input |
| SPI2_MOSI_OE | 1 | output |
| SPI2_MOSI_OUT | 1 | output |
| SPI2_WPN_IN | 1 | input |
| SPI2_WPN_OE | 1 | output |
| SPI2_WPN_OUT | 1 | output |
| TDI_IN | 1 | input |
| TDO_OE | 1 | output |
| TDO_OUT | 1 | output |
| TEST_CLK | 1 | input |
| TEST_MODE | 1 | input |
| TEST_RSTN | 1 | input |
| TMS_IN | 1 | input |
| TRST_IN | 1 | input |
| UART1_CTSN | 1 | input |
| UART1_DCDN | 1 | input |
| UART1_DSRN | 1 | input |
| UART1_DTRN | 1 | output |
| UART1_OUT1N | 1 | output |
| UART1_OUT2N | 1 | output |
| UART1_RIN | 1 | input |
| UART1_RTSN | 1 | output |
| UART1_RXD | 1 | input |
| UART1_TXD | 1 | output |
| UART2_CTSN | 1 | input |
| UART2_DCDN | 1 | input |
| UART2_DSRN | 1 | input |
| UART2_DTRN | 1 | output |
| UART2_OUT1N | 1 | output |
| UART2_OUT2N | 1 | output |
| UART2_RIN | 1 | input |
| UART2_RTSN | 1 | output |
| UART2_RXD | 1 | input |
| UART2_TXD | 1 | output |
| WAKEUP_IN | 1 | input |
AE350_SOC ae350_soc_inst (
.AHB_CE(AHB_CE),
.AHB_CLK(AHB_CLK),
.APB2AHB_CE(APB2AHB_CE),
.APB_CE(APB_CE),
.APB_CLK(APB_CLK),
.APB_PADDR(APB_PADDR),
.APB_PENABLE(APB_PENABLE),
.APB_PPROT(APB_PPROT),
.APB_PRDATA(APB_PRDATA),
.APB_PREADY(APB_PREADY),
.APB_PSEL(APB_PSEL),
.APB_PSLVERR(APB_PSLVERR),
.APB_PSTRB(APB_PSTRB),
.APB_PWDATA(APB_PWDATA),
.APB_PWRITE(APB_PWRITE),
.AXI_CE(AXI_CE),
.CH0_PWM(CH0_PWM),
.CH0_PWMOE(CH0_PWMOE),
.CH1_PWM(CH1_PWM),
.CH1_PWMOE(CH1_PWMOE),
.CH2_PWM(CH2_PWM),
.CH2_PWMOE(CH2_PWMOE),
.CH3_PWM(CH3_PWM),
.CH3_PWMOE(CH3_PWMOE),
.CORE0_WFI_MODE(CORE0_WFI_MODE),
.CORE_CE(CORE_CE),
.CORE_CLK(CORE_CLK),
.DBG_TCK(DBG_TCK),
.DDR_CE(DDR_CE),
.DDR_CLK(DDR_CLK),
.DDR_HADDR(DDR_HADDR),
.DDR_HBURST(DDR_HBURST),
.DDR_HPROT(DDR_HPROT),
.DDR_HRDATA(DDR_HRDATA),
.DDR_HREADY(DDR_HREADY),
.DDR_HRESP(DDR_HRESP),
.DDR_HSIZE(DDR_HSIZE),
.DDR_HTRANS(DDR_HTRANS),
.DDR_HWDATA(DDR_HWDATA),
.DDR_HWRITE(DDR_HWRITE),
.DDR_RSTN(DDR_RSTN),
.DMA_ACK(DMA_ACK),
.DMA_REQ(DMA_REQ),
.EMA(EMA),
.EMAS(EMAS),
.EMAW(EMAW),
.EXTM_HADDR(EXTM_HADDR),
.EXTM_HBURST(EXTM_HBURST),
.EXTM_HPROT(EXTM_HPROT),
.EXTM_HRDATA(EXTM_HRDATA),
.EXTM_HREADY(EXTM_HREADY),
.EXTM_HREADYOUT(EXTM_HREADYOUT),
.EXTM_HRESP(EXTM_HRESP),
.EXTM_HSEL(EXTM_HSEL),
.EXTM_HSIZE(EXTM_HSIZE),
.EXTM_HTRANS(EXTM_HTRANS),
.EXTM_HWDATA(EXTM_HWDATA),
.EXTM_HWRITE(EXTM_HWRITE),
.EXTS_HADDR(EXTS_HADDR),
.EXTS_HBURST(EXTS_HBURST),
.EXTS_HPROT(EXTS_HPROT),
.EXTS_HRDATA(EXTS_HRDATA),
.EXTS_HREADYIN(EXTS_HREADYIN),
.EXTS_HRESP(EXTS_HRESP),
.EXTS_HSEL(EXTS_HSEL),
.EXTS_HSIZE(EXTS_HSIZE),
.EXTS_HTRANS(EXTS_HTRANS),
.EXTS_HWDATA(EXTS_HWDATA),
.EXTS_HWRITE(EXTS_HWRITE),
.GPIO_IN(GPIO_IN),
.GPIO_OE(GPIO_OE),
.GPIO_OUT(GPIO_OUT),
.GP_INT(GP_INT),
.HRESETN(HRESETN),
.HW_RSTN(HW_RSTN),
.I2C_SCL(I2C_SCL),
.I2C_SCL_IN(I2C_SCL_IN),
.I2C_SDA(I2C_SDA),
.I2C_SDA_IN(I2C_SDA_IN),
.INTEG_TCK(INTEG_TCK),
.INTEG_TDI(INTEG_TDI),
.INTEG_TDO(INTEG_TDO),
.INTEG_TMS(INTEG_TMS),
.INTEG_TRST(INTEG_TRST),
.PGEN_CHAIN_I(PGEN_CHAIN_I),
.POR_N(POR_N),
.PRDYN_CHAIN_O(PRDYN_CHAIN_O),
.PRESETN(PRESETN),
.RET1N(RET1N),
.RET2N(RET2N),
.ROM_HADDR(ROM_HADDR),
.ROM_HRDATA(ROM_HRDATA),
.ROM_HREADY(ROM_HREADY),
.ROM_HRESP(ROM_HRESP),
.ROM_HTRANS(ROM_HTRANS),
.ROM_HWRITE(ROM_HWRITE),
.RTC_CLK(RTC_CLK),
.RTC_WAKEUP(RTC_WAKEUP),
.SCAN_EN(SCAN_EN),
.SCAN_IN(SCAN_IN),
.SCAN_OUT(SCAN_OUT),
.SCAN_TEST(SCAN_TEST),
.SPI2_CLK_IN(SPI2_CLK_IN),
.SPI2_CLK_OE(SPI2_CLK_OE),
.SPI2_CLK_OUT(SPI2_CLK_OUT),
.SPI2_CSN_IN(SPI2_CSN_IN),
.SPI2_CSN_OE(SPI2_CSN_OE),
.SPI2_CSN_OUT(SPI2_CSN_OUT),
.SPI2_HOLDN_IN(SPI2_HOLDN_IN),
.SPI2_HOLDN_OE(SPI2_HOLDN_OE),
.SPI2_HOLDN_OUT(SPI2_HOLDN_OUT),
.SPI2_MISO_IN(SPI2_MISO_IN),
.SPI2_MISO_OE(SPI2_MISO_OE),
.SPI2_MISO_OUT(SPI2_MISO_OUT),
.SPI2_MOSI_IN(SPI2_MOSI_IN),
.SPI2_MOSI_OE(SPI2_MOSI_OE),
.SPI2_MOSI_OUT(SPI2_MOSI_OUT),
.SPI2_WPN_IN(SPI2_WPN_IN),
.SPI2_WPN_OE(SPI2_WPN_OE),
.SPI2_WPN_OUT(SPI2_WPN_OUT),
.TDI_IN(TDI_IN),
.TDO_OE(TDO_OE),
.TDO_OUT(TDO_OUT),
.TEST_CLK(TEST_CLK),
.TEST_MODE(TEST_MODE),
.TEST_RSTN(TEST_RSTN),
.TMS_IN(TMS_IN),
.TRST_IN(TRST_IN),
.UART1_CTSN(UART1_CTSN),
.UART1_DCDN(UART1_DCDN),
.UART1_DSRN(UART1_DSRN),
.UART1_DTRN(UART1_DTRN),
.UART1_OUT1N(UART1_OUT1N),
.UART1_OUT2N(UART1_OUT2N),
.UART1_RIN(UART1_RIN),
.UART1_RTSN(UART1_RTSN),
.UART1_RXD(UART1_RXD),
.UART1_TXD(UART1_TXD),
.UART2_CTSN(UART2_CTSN),
.UART2_DCDN(UART2_DCDN),
.UART2_DSRN(UART2_DSRN),
.UART2_DTRN(UART2_DTRN),
.UART2_OUT1N(UART2_OUT1N),
.UART2_OUT2N(UART2_OUT2N),
.UART2_RIN(UART2_RIN),
.UART2_RTSN(UART2_RTSN),
.UART2_RXD(UART2_RXD),
.UART2_TXD(UART2_TXD),
.WAKEUP_IN(WAKEUP_IN)
);