IVIDEO

The 1 to 7 Deserializer (IVIDEO) is a deserializer that converts 1 bit serial input into 7 bits parallel output. It realizes 1:7 serial parallel conversion, providing output data to FPGA logic at the same clock edge. The data is shifted by two bits per pulse, and after seven shifts, the output data will be the same as the input data before the shift. The IVIDEO primitive also supports CALIB signal to adjust the sequence of output data and uses FCLK frequency division to obtain PCLK.

This device is supported in Apicula.

Ports

Port	Size	Direction
CALIB	1	input
D	1	input
FCLK	1	input
PCLK	1	input
Q0	1	output
Q1	1	output
Q2	1	output
Q3	1	output
Q4	1	output
Q5	1	output
Q6	1	output
RESET	1	input

Parameters

Parameter	Default Value
GSREN	false
LSREN	true

Verilog Instantiation

IVIDEO #(
    .GSREN(GSREN),
    .LSREN(LSREN)
) ivideo_inst (
    .CALIB(CALIB),
    .D(D),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .Q2(Q2),
    .Q3(Q3),
    .Q4(Q4),
    .Q5(Q5),
    .Q6(Q6),
    .RESET(RESET)
);