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Pepijn de Vos edited this page Nov 19, 2024 · 2 revisions

MUX16

This device is not yet supported in Apicula

Ports

Port Size Direction
I0 1 input
I1 1 input
I10 1 input
I11 1 input
I12 1 input
I13 1 input
I14 1 input
I15 1 input
I2 1 input
I3 1 input
I4 1 input
I5 1 input
I6 1 input
I7 1 input
I8 1 input
I9 1 input
O 1 output
S0 1 input
S1 1 input
S2 1 input
S3 1 input

Verilog Instantiation

MUX16 mux16_inst (
    .I0(I0),
    .I1(I1),
    .I10(I10),
    .I11(I11),
    .I12(I12),
    .I13(I13),
    .I14(I14),
    .I15(I15),
    .I2(I2),
    .I3(I3),
    .I4(I4),
    .I5(I5),
    .I6(I6),
    .I7(I7),
    .I8(I8),
    .I9(I9),
    .O(O),
    .S0(S0),
    .S1(S1),
    .S2(S2),
    .S3(S3)
);

MUX2

The Gowin MUX2 primitive is a 2-to-1 multiplexer that selects one of two inputs as the output based on a selection signal, also referred to as the channel-selection signal or selection signal. The primitive has four ports: I0 and I1 for the input data, S0 for the selection signal, and O for the output data. Its truth table shows that when S0 is 0, I0 is transmitted to the output, and when S0 is 1, I1 is transmitted to the output. The primitive can be instantiated in a Verilog module using the specified syntax.

This device is not yet supported in Apicula

Ports

Port Size Direction
I0 1 input
I1 1 input
O 1 output
S0 1 input

Verilog Instantiation

MUX2 mux2_inst (
    .I0(I0),
    .I1(I1),
    .O(O),
    .S0(S0)
);

MUX2_LUT5

This device is supported in Apicula.

Ports

Port Size Direction
I0 1 input
I1 1 input
O 1 output
S0 1 input

Verilog Instantiation

MUX2_LUT5 mux2_lut5_inst (
    .I0(I0),
    .I1(I1),
    .O(O),
    .S0(S0)
);

MUX2_LUT6

This device is supported in Apicula.

Ports

Port Size Direction
I0 1 input
I1 1 input
O 1 output
S0 1 input

Verilog Instantiation

MUX2_LUT6 mux2_lut6_inst (
    .I0(I0),
    .I1(I1),
    .O(O),
    .S0(S0)
);

MUX2_LUT7

This device is supported in Apicula.

Ports

Port Size Direction
I0 1 input
I1 1 input
O 1 output
S0 1 input

Verilog Instantiation

MUX2_LUT7 mux2_lut7_inst (
    .I0(I0),
    .I1(I1),
    .O(O),
    .S0(S0)
);

MUX2_LUT8

This device is supported in Apicula.

Ports

Port Size Direction
I0 1 input
I1 1 input
O 1 output
S0 1 input

Verilog Instantiation

MUX2_LUT8 mux2_lut8_inst (
    .I0(I0),
    .I1(I1),
    .O(O),
    .S0(S0)
);

MUX2_MUX16

This device is not yet supported in Apicula

Ports

Port Size Direction
I0 1 input
I1 1 input
O 1 output
S0 1 input

Verilog Instantiation

MUX2_MUX16 mux2_mux16_inst (
    .I0(I0),
    .I1(I1),
    .O(O),
    .S0(S0)
);

MUX2_MUX32

This device is not yet supported in Apicula

Ports

Port Size Direction
I0 1 input
I1 1 input
O 1 output
S0 1 input

Verilog Instantiation

MUX2_MUX32 mux2_mux32_inst (
    .I0(I0),
    .I1(I1),
    .O(O),
    .S0(S0)
);

MUX2_MUX8

This device is not yet supported in Apicula

Ports

Port Size Direction
I0 1 input
I1 1 input
O 1 output
S0 1 input

Verilog Instantiation

MUX2_MUX8 mux2_mux8_inst (
    .I0(I0),
    .I1(I1),
    .O(O),
    .S0(S0)
);

MUX32

This device is not yet supported in Apicula

Ports

Port Size Direction
I0 1 input
I1 1 input
I10 1 input
I11 1 input
I12 1 input
I13 1 input
I14 1 input
I15 1 input
I16 1 input
I17 1 input
I18 1 input
I19 1 input
I2 1 input
I20 1 input
I21 1 input
I22 1 input
I23 1 input
I24 1 input
I25 1 input
I26 1 input
I27 1 input
I28 1 input
I29 1 input
I3 1 input
I30 1 input
I31 1 input
I4 1 input
I5 1 input
I6 1 input
I7 1 input
I8 1 input
I9 1 input
O 1 output
S0 1 input
S1 1 input
S2 1 input
S3 1 input
S4 1 input

Verilog Instantiation

MUX32 mux32_inst (
    .I0(I0),
    .I1(I1),
    .I10(I10),
    .I11(I11),
    .I12(I12),
    .I13(I13),
    .I14(I14),
    .I15(I15),
    .I16(I16),
    .I17(I17),
    .I18(I18),
    .I19(I19),
    .I2(I2),
    .I20(I20),
    .I21(I21),
    .I22(I22),
    .I23(I23),
    .I24(I24),
    .I25(I25),
    .I26(I26),
    .I27(I27),
    .I28(I28),
    .I29(I29),
    .I3(I3),
    .I30(I30),
    .I31(I31),
    .I4(I4),
    .I5(I5),
    .I6(I6),
    .I7(I7),
    .I8(I8),
    .I9(I9),
    .O(O),
    .S0(S0),
    .S1(S1),
    .S2(S2),
    .S3(S3),
    .S4(S4)
);

MUX4

The Gowin MUX4 primitive is a 4-to-1 multiplexer that selects one of the four inputs as the output based on two selection signals, S0 and S1. It has five ports: I0, I1, I2, and I3 are input data inputs, while O is the output. The primitive is instantiated in VHDL using a COMPONENT statement, where the MUX4 component is connected to the uut port map with the corresponding input/output signals.

This device is not yet supported in Apicula

Ports

Port Size Direction
I0 1 input
I1 1 input
I2 1 input
I3 1 input
O 1 output
S0 1 input
S1 1 input

Verilog Instantiation

MUX4 mux4_inst (
    .I0(I0),
    .I1(I1),
    .I2(I2),
    .I3(I3),
    .O(O),
    .S0(S0),
    .S1(S1)
);

MUX8

This device is not yet supported in Apicula

Ports

Port Size Direction
I0 1 input
I1 1 input
I2 1 input
I3 1 input
I4 1 input
I5 1 input
I6 1 input
I7 1 input
O 1 output
S0 1 input
S1 1 input
S2 1 input

Verilog Instantiation

MUX8 mux8_inst (
    .I0(I0),
    .I1(I1),
    .I2(I2),
    .I3(I3),
    .I4(I4),
    .I5(I5),
    .I6(I6),
    .I7(I7),
    .O(O),
    .S0(S0),
    .S1(S1),
    .S2(S2)
);
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