AE350_RAM

This device is not yet supported in Apicula

Ports

Port	Size	Direction
AHB_CE	1	input
AHB_CLK	1	input
APB_CLK	1	input
AXI_CE	1	input
CORE_CE	1	input
CORE_CLK	1	input
EMA	3	input
EMAS	1	input
EMAW	2	input
EXTM_HADDR	32	input
EXTM_HBURST	3	input
EXTM_HPROT	4	input
EXTM_HRDATA	64	output
EXTM_HREADY	1	input
EXTM_HREADYOUT	1	output
EXTM_HRESP	1	output
EXTM_HSEL	1	input
EXTM_HSIZE	3	input
EXTM_HTRANS	2	input
EXTM_HWDATA	64	input
EXTM_HWRITE	1	input
HW_RSTN	1	input
POR_N	1	input
RET1N	1	input
RET2N	1	input
RTC_CLK	1	input

Verilog Instantiation

AE350_RAM ae350_ram_inst (
    .AHB_CE(AHB_CE),
    .AHB_CLK(AHB_CLK),
    .APB_CLK(APB_CLK),
    .AXI_CE(AXI_CE),
    .CORE_CE(CORE_CE),
    .CORE_CLK(CORE_CLK),
    .EMA(EMA),
    .EMAS(EMAS),
    .EMAW(EMAW),
    .EXTM_HADDR(EXTM_HADDR),
    .EXTM_HBURST(EXTM_HBURST),
    .EXTM_HPROT(EXTM_HPROT),
    .EXTM_HRDATA(EXTM_HRDATA),
    .EXTM_HREADY(EXTM_HREADY),
    .EXTM_HREADYOUT(EXTM_HREADYOUT),
    .EXTM_HRESP(EXTM_HRESP),
    .EXTM_HSEL(EXTM_HSEL),
    .EXTM_HSIZE(EXTM_HSIZE),
    .EXTM_HTRANS(EXTM_HTRANS),
    .EXTM_HWDATA(EXTM_HWDATA),
    .EXTM_HWRITE(EXTM_HWRITE),
    .HW_RSTN(HW_RSTN),
    .POR_N(POR_N),
    .RET1N(RET1N),
    .RET2N(RET2N),
    .RTC_CLK(RTC_CLK)
);