DHCE

DHCE

The Gowin DHCE primitive can be used to dynamically turn on/off the HCLK signal, and it has three ports: CLKIN (clock input), CEN (clock enable, active-low), and CLKOUT (clock output). The primitive can be instantiated directly in a design using either Verilog or VHDL.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
CEN	1	input
CLKIN	1	input
CLKOUT	1	output

Verilog Instantiation

DHCE dhce_inst (
    .CEN(CEN),
    .CLKIN(CLKIN),
    .CLKOUT(CLKOUT)
);

DHCEN

The DHCEN primitive allows for dynamic control over the HCLK signal, enabling it to be turned on or off. It is conductive when the CE (Clock Enable) input is low, making it suitable for applications where clock enable functionality is required. The output of DHCEN can be connected to various clocks in different devices, such as IOLOGIC, CLKDIV, DQS, PLL/PLLVR/PLLO, DCC, DCCG, and CLKDIV2, to control the HCLK signal in those devices.

This device is supported in Apicula.

Ports

Port	Size	Direction
CE	1	input
CLKIN	1	input
CLKOUT	1	output

Verilog Instantiation

DHCEN dhcen_inst (
    .CE(CE),
    .CLKIN(CLKIN),
    .CLKOUT(CLKOUT)
);

DHCENC

The DHCENC primitive allows for dynamic on/off control of HCLK through CE, where it is conductive when CE is low. It can be used with a variety of clock output signals (CLKOUT and CLKOUTN) to produce complementary clock outputs. The primitive is supported by specific devices in the Gowin family and can be instantiated directly or generated by an IP Core Generator tool.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
CE	1	input
CLKIN	1	input
CLKOUT	1	output
CLKOUTN	1	output

Verilog Instantiation

DHCENC dhcenc_inst (
    .CE(CE),
    .CLKIN(CLKIN),
    .CLKOUT(CLKOUT),
    .CLKOUTN(CLKOUTN)
);