LUT

LUT1

The LUT1 primitive is a 1-input look-up table, used as a buffer and an inverter. After initialization, it can be looked up according to the input address, then outputting the corresponding data. It has one input (I0) and one output (F), with the initial value of LUT1 being set from 2'h0 to 2'h3 by default, as specified by the INIT parameter.

This device is supported in Apicula.

Ports

Port	Size	Direction
F	1	output
I0	1	input

Parameters

Parameter	Default Value
INIT	0 (0b00)

Verilog Instantiation

LUT1 #(
    .INIT(INIT)
) lut1_inst (
    .F(F),
    .I0(I0)
);

LUT2

The LUT2 primitive is a 2-input look-up table that allows you to look up corresponding data according to the input address after initializing, then it outputs the data.

This device is supported in Apicula.

Ports

Port	Size	Direction
F	1	output
I0	1	input
I1	1	input

Parameters

Parameter	Default Value
INIT	0 (0b0000)

Verilog Instantiation

LUT2 #(
    .INIT(INIT)
) lut2_inst (
    .F(F),
    .I0(I0),
    .I1(I1)
);

LUT3

LUT3 is a 3-input look-up table. After initializing, you can look up the corresponding data according to the input address, then it outputs the data.

This device is supported in Apicula.

Ports

Port	Size	Direction
F	1	output
I0	1	input
I1	1	input
I2	1	input

Parameters

Parameter	Default Value
INIT	0 (0b00000000)

Verilog Instantiation

LUT3 #(
    .INIT(INIT)
) lut3_inst (
    .F(F),
    .I0(I0),
    .I1(I1),
    .I2(I2)
);

LUT4

The Gowin LUT4 primitive is a 4-input look-up table that stores 16-bit data. After initialization, it allows for data lookup based on a 4-bit input address, outputting the corresponding 16-bit data value. The LUT4 has four inputs (I0-I3) and one output (F), with an optional parameter (INIT) to set the initial contents of the table from 0 to 65535 (hexadecimal values 0000 to ffff).

This device is supported in Apicula.

Ports

Port	Size	Direction
F	1	output
I0	1	input
I1	1	input
I2	1	input
I3	1	input

Parameters

Parameter	Default Value
INIT	0 (0b0000000000000000)

Verilog Instantiation

LUT4 #(
    .INIT(INIT)
) lut4_inst (
    .F(F),
    .I0(I0),
    .I1(I1),
    .I2(I2),
    .I3(I3)
);

LUT5

This device is not yet supported in Apicula

Ports

Port	Size	Direction
F	1	output
I0	1	input
I1	1	input
I2	1	input
I3	1	input
I4	1	input

Parameters

Parameter	Default Value
INIT	0 (0b00000000000000000000000000000000)

Verilog Instantiation

LUT5 #(
    .INIT(INIT)
) lut5_inst (
    .F(F),
    .I0(I0),
    .I1(I1),
    .I2(I2),
    .I3(I3),
    .I4(I4)
);

LUT6

This device is not yet supported in Apicula

Ports

Port	Size	Direction
F	1	output
I0	1	input
I1	1	input
I2	1	input
I3	1	input
I4	1	input
I5	1	input

Parameters

Parameter	Default Value
INIT	0 (0b0000000000000000000000000000000000000000000000000000000000000000)

Verilog Instantiation

LUT6 #(
    .INIT(INIT)
) lut6_inst (
    .F(F),
    .I0(I0),
    .I1(I1),
    .I2(I2),
    .I3(I3),
    .I4(I4),
    .I5(I5)
);

LUT7

This device is not yet supported in Apicula

Ports

Port	Size	Direction
F	1	output
I0	1	input
I1	1	input
I2	1	input
I3	1	input
I4	1	input
I5	1	input
I6	1	input

Parameters

Parameter	Default Value
INIT	0 (0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000)

Verilog Instantiation

LUT7 #(
    .INIT(INIT)
) lut7_inst (
    .F(F),
    .I0(I0),
    .I1(I1),
    .I2(I2),
    .I3(I3),
    .I4(I4),
    .I5(I5),
    .I6(I6)
);

LUT8

This device is not yet supported in Apicula

Ports

Port	Size	Direction
F	1	output
I0	1	input
I1	1	input
I2	1	input
I3	1	input
I4	1	input
I5	1	input
I6	1	input
I7	1	input

Parameters

Parameter	Default Value
INIT	0 (0b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000)

Verilog Instantiation

LUT8 #(
    .INIT(INIT)
) lut8_inst (
    .F(F),
    .I0(I0),
    .I1(I1),
    .I2(I2),
    .I3(I3),
    .I4(I4),
    .I5(I5),
    .I6(I6),
    .I7(I7)
);