IEM

The IEM (Input Edge Monitor) primitive is a sampling module used for detecting data edge, which can be used in conjunction with a delay module to adjust the dynamic sampling window for DDR mode. It has two output flags: LAG and LEAD, indicating the lag or lead position of the input data edge relative to the clock signal, and it can also detect an asynchronous reset input signal and generate flags based on user-provided clock signals (MCLK).

This device is not yet supported in Apicula

Ports

Port	Size	Direction
CLK	1	input
D	1	input
LAG	1	output
LEAD	1	output
MCLK	1	input
RESET	1	input

Parameters

Parameter	Default Value
GSREN	false
LSREN	true
WINSIZE	SMALL

Verilog Instantiation

IEM #(
    .GSREN(GSREN),
    .LSREN(LSREN),
    .WINSIZE(WINSIZE)
) iem_inst (
    .CLK(CLK),
    .D(D),
    .LAG(LAG),
    .LEAD(LEAD),
    .MCLK(MCLK),
    .RESET(RESET)
);