RAM16S

RAM16S1

The RAM16S1 primitive is a single-port SSRAM with an address depth of 16 and a data width of 1. It has synchronous write operation, where data is loaded into the corresponding memory address at the rising edge of the clock (CLK) when the Write Enable (WRE) signal is high. The read and write addresses are the same, and during read operation, the data stored in RAM is retrieved based on the specified address.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
AD	4	input
CLK	1	input
DI	1	input
DO	1	output
WRE	1	input

Parameters

Parameter	Default Value
INIT_0	0 (0b0000000000000000)

Verilog Instantiation

RAM16S1 #(
    .INIT_0(INIT_0)
) ram16s1_inst (
    .AD(AD),
    .CLK(CLK),
    .DI(DI),
    .DO(DO),
    .WRE(WRE)
);

RAM16S2

The RAM16S2 is a single-port SSRAM (Static Shift Register Array Memory) with 16 address depth and 2-bit data width. It has synchronous write and asynchronous read operations, implemented using LUTs in the CFU. The write operation is performed when WRE (Write Enable) is high, at the rising edge of CLK, while the read operation reads the data specified by the address corresponding to the data stored in RAM.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
AD	4	input
CLK	1	input
DI	2	input
DO	2	output
WRE	1	input

Parameters

Parameter	Default Value
INIT_0	0 (0b0000000000000000)
INIT_1	0 (0b0000000000000000)

Verilog Instantiation

RAM16S2 #(
    .INIT_0(INIT_0),
    .INIT_1(INIT_1)
) ram16s2_inst (
    .AD(AD),
    .CLK(CLK),
    .DI(DI),
    .DO(DO),
    .WRE(WRE)
);

RAM16S4

The RAM16S4 primitive is a single-port SSRAM with 16 address depth and 4-bit data width. It allows for both synchronous write and asynchronous read operations, with the same address used for both read and write operations. When WRE (Write Enable) is high, the data is loaded into the corresponding address in the memory at the rising edge of CLK (Clock). In a read operation, the data stored in RAM is read out based on the address specified.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
AD	4	input
CLK	1	input
DI	4	input
DO	4	output
WRE	1	input

Parameters

Parameter	Default Value
INIT_0	0 (0b0000000000000000)
INIT_1	0 (0b0000000000000000)
INIT_2	0 (0b0000000000000000)
INIT_3	0 (0b0000000000000000)

Verilog Instantiation

RAM16S4 #(
    .INIT_0(INIT_0),
    .INIT_1(INIT_1),
    .INIT_2(INIT_2),
    .INIT_3(INIT_3)
) ram16s4_inst (
    .AD(AD),
    .CLK(CLK),
    .DI(DI),
    .DO(DO),
    .WRE(WRE)
);

RAM16SDP1

The RAM16SDP1 primitive is a semi-dual-port SSRAM with 16 address depth and 1-bit data width. It has two asynchronous addresses, write address WAD and read address RAD. The write operation is performed when WRE is high, at the rising edge of CLK, loading data into the corresponding write address in memory. The read operation determines the output data by the read address, with no timing diagram provided to illustrate this functionality.

This device is supported in Apicula

Ports

Port	Size	Direction
CLK	1	input
DI	1	input
DO	1	output
RAD	4	input
WAD	4	input
WRE	1	input

Parameters

Parameter	Default Value
INIT_0	0 (0b0000000000000000)

Verilog Instantiation

RAM16SDP1 #(
    .INIT_0(INIT_0)
) ram16sdp1_inst (
    .CLK(CLK),
    .DI(DI),
    .DO(DO),
    .RAD(RAD),
    .WAD(WAD),
    .WRE(WRE)
);

RAM16SDP2

The RAM16SDP2 is a semi-dual-port SSRAM with 16 address depth and 2-bit data width. It has two asynchronous addresses, write address WAD and read address RAD. The write operation is performed when WRE is high, at which time the data is loaded into the corresponding write address of the memory at the rising edge of CLK. The read operation is based on the read address to determine the data in the corresponding location of the output RAM.

This device is supported in Apicula

Ports

Port	Size	Direction
CLK	1	input
DI	2	input
DO	2	output
RAD	4	input
WAD	4	input
WRE	1	input

Parameters

Parameter	Default Value
INIT_0	0 (0b0000000000000000)
INIT_1	0 (0b0000000000000000)

Verilog Instantiation

RAM16SDP2 #(
    .INIT_0(INIT_0),
    .INIT_1(INIT_1)
) ram16sdp2_inst (
    .CLK(CLK),
    .DI(DI),
    .DO(DO),
    .RAD(RAD),
    .WAD(WAD),
    .WRE(WRE)
);

RAM16SDP4

The Gowin RAM16SDP4 primitive is a semi-dual-port SSRAM with 16 address depth and 4-bit data width. It has two asynchronous addresses, write address WAD and read address RAD, and performs write operations when WRE is high at the rising edge of CLK, loading data into the corresponding write address in the memory. Read operations are based on the read address to determine data in the corresponding location for output in the RAM.

This device is supported in Apicula.

Ports

Port	Size	Direction
CLK	1	input
DI	4	input
DO	4	output
RAD	4	input
WAD	4	input
WRE	1	input

Parameters

Parameter	Default Value
INIT_0	0 (0b0000000000000000)
INIT_1	0 (0b0000000000000000)
INIT_2	0 (0b0000000000000000)
INIT_3	0 (0b0000000000000000)

Verilog Instantiation

RAM16SDP4 #(
    .INIT_0(INIT_0),
    .INIT_1(INIT_1),
    .INIT_2(INIT_2),
    .INIT_3(INIT_3)
) ram16sdp4_inst (
    .CLK(CLK),
    .DI(DI),
    .DO(DO),
    .RAD(RAD),
    .WAD(WAD),
    .WRE(WRE)
);