ODDR

ODDR

The ODDR (ODDR) primitive, also known as Dual Data Rate Output, is used for transferring double data rate signals from FPGA devices. The Q0 output is the double rate data output, while Q1 is used for the OEN signal of an IOBUF/TBUF connected by Q1.

This device is supported in Apicula.

Ports

Port	Size	Direction
CLK	1	input
D0	1	input
D1	1	input
Q0	1	output
Q1	1	output
TX	1	input

Parameters

Parameter	Default Value
INIT	0 (0b00000000000000000000000000000000)
TXCLK_POL	0 (0b00000000000000000000000000000000)

Verilog Instantiation

ODDR #(
    .INIT(INIT),
    .TXCLK_POL(TXCLK_POL)
) oddr_inst (
    .CLK(CLK),
    .D0(D0),
    .D1(D1),
    .Q0(Q0),
    .Q1(Q1),
    .TX(TX)
);

ODDRC

The ODDRC primitive transfers double data rate signals from FPGA devices, where Q0 is a double rate data output and Q1 is used for the OEN signal of IOBUF/TBUF connected to Q1. The logic diagram shows DFFC and DFFNC components, MUX2 logic, and other elements that generate Q0 and Q1 outputs based on inputs D0, D1, TX, CLK, and CLEAR signals.

This device is supported in Apicula.

Ports

Port	Size	Direction
CLEAR	1	input
CLK	1	input
D0	1	input
D1	1	input
Q0	1	output
Q1	1	output
TX	1	input

Parameters

Parameter	Default Value
INIT	0 (0b00000000000000000000000000000000)
TXCLK_POL	0 (0b00000000000000000000000000000000)

Verilog Instantiation

ODDRC #(
    .INIT(INIT),
    .TXCLK_POL(TXCLK_POL)
) oddrc_inst (
    .CLEAR(CLEAR),
    .CLK(CLK),
    .D0(D0),
    .D1(D1),
    .Q0(Q0),
    .Q1(Q1),
    .TX(TX)
);

ODDR_MEM

The ODDR_MEM (Dual Data Rate Output with Memory) primitive, supported by the Gowin library, enables double data rate output with memory. It is used for transferring double data rate signals from FPGA devices, requiring the use of DQS (Data Strobe) signals. The TCLK input connects to either DQSW0 or DQSW270 of the DQS output signal and outputs data according to the TCLK clock edge. Two primary outputs are provided: Q0 (double rate data output) and Q1 (used for the OEN signal of IOBUF/TBUF connected to Q0). The frequency relationship between PCLK and TCLK is PCLK = TCLK/ff, where ff is a scaling factor that must be provided separately.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
D0	1	input
D1	1	input
PCLK	1	input
Q0	1	output
Q1	1	output
RESET	1	input
TCLK	1	input
TX	1	input

Parameters

Parameter	Default Value
TCLK_SOURCE	DQSW
TXCLK_POL	0 (0b0)

Verilog Instantiation

ODDR_MEM #(
    .TCLK_SOURCE(TCLK_SOURCE),
    .TXCLK_POL(TXCLK_POL)
) oddr_mem_inst (
    .D0(D0),
    .D1(D1),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .RESET(RESET),
    .TCLK(TCLK),
    .TX(TX)
);