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PLL
Pepijn de Vos edited this page Nov 19, 2024
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The PLL (Phase-Locked Loop) primitive supports independent adjustment of clock frequency, phase, and duty cycle based on a given reference input clock. It provides seven clock outputs, each of which can be configured separately to suit specific design requirements. The PLL structure diagram is as shown in Figure 5-1.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| CLKFB | 1 | input |
| CLKFBOUT | 1 | output |
| CLKIN | 1 | input |
| CLKOUT0 | 1 | output |
| CLKOUT1 | 1 | output |
| CLKOUT2 | 1 | output |
| CLKOUT3 | 1 | output |
| CLKOUT4 | 1 | output |
| CLKOUT5 | 1 | output |
| CLKOUT6 | 1 | output |
| DT0 | 4 | input |
| DT1 | 4 | input |
| DT2 | 4 | input |
| DT3 | 4 | input |
| ENCLK0 | 1 | input |
| ENCLK1 | 1 | input |
| ENCLK2 | 1 | input |
| ENCLK3 | 1 | input |
| ENCLK4 | 1 | input |
| ENCLK5 | 1 | input |
| ENCLK6 | 1 | input |
| FBDSEL | 6 | input |
| ICPSEL | 6 | input |
| IDSEL | 6 | input |
| LOCK | 1 | output |
| LPFCAP | 2 | input |
| LPFRES | 3 | input |
| MDSEL | 7 | input |
| MDSEL_FRAC | 3 | input |
| ODSEL0 | 7 | input |
| ODSEL0_FRAC | 3 | input |
| ODSEL1 | 7 | input |
| ODSEL2 | 7 | input |
| ODSEL3 | 7 | input |
| ODSEL4 | 7 | input |
| ODSEL5 | 7 | input |
| ODSEL6 | 7 | input |
| PLLPWD | 1 | input |
| PSDIR | 1 | input |
| PSPULSE | 1 | input |
| PSSEL | 3 | input |
| RESET | 1 | input |
| RESET_I | 1 | input |
| RESET_O | 1 | input |
| SSCMDSEL | 7 | input |
| SSCMDSEL_FRAC | 3 | input |
| SSCON | 1 | input |
| SSCPOL | 1 | input |
| Parameter | Default Value |
|---|---|
| CLK0_IN_SEL | 0 (0b0) |
| CLK0_OUT_SEL | 0 (0b0) |
| CLK1_IN_SEL | 0 (0b0) |
| CLK1_OUT_SEL | 0 (0b0) |
| CLK2_IN_SEL | 0 (0b0) |
| CLK2_OUT_SEL | 0 (0b0) |
| CLK3_IN_SEL | 0 (0b0) |
| CLK3_OUT_SEL | 0 (0b0) |
| CLK4_IN_SEL | 0 (0b00) |
| CLK4_OUT_SEL | 0 (0b0) |
| CLK5_IN_SEL | 0 (0b0) |
| CLK5_OUT_SEL | 0 (0b0) |
| CLK6_IN_SEL | 0 (0b0) |
| CLK6_OUT_SEL | 0 (0b0) |
| CLKFB_SEL | INTERNAL |
| CLKOUT0_DT_DIR | 1 (0b1) |
| CLKOUT0_DT_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUT0_EN | TRUE |
| CLKOUT0_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT0_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT1_DT_DIR | 1 (0b1) |
| CLKOUT1_DT_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUT1_EN | FALSE |
| CLKOUT1_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT1_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT2_DT_DIR | 1 (0b1) |
| CLKOUT2_DT_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUT2_EN | FALSE |
| CLKOUT2_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT2_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT3_DT_DIR | 1 (0b1) |
| CLKOUT3_DT_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUT3_EN | FALSE |
| CLKOUT3_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT3_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT4_EN | FALSE |
| CLKOUT4_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT4_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT5_EN | FALSE |
| CLKOUT5_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT5_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT6_EN | FALSE |
| CLKOUT6_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT6_PE_FINE | 0 (0b00000000000000000000000000000000) |
| DE0_EN | FALSE |
| DE1_EN | FALSE |
| DE2_EN | FALSE |
| DE3_EN | FALSE |
| DE4_EN | FALSE |
| DE5_EN | FALSE |
| DE6_EN | FALSE |
| DYN_DPA_EN | FALSE |
| DYN_DT0_SEL | FALSE |
| DYN_DT1_SEL | FALSE |
| DYN_DT2_SEL | FALSE |
| DYN_DT3_SEL | FALSE |
| DYN_FBDIV_SEL | FALSE |
| DYN_ICP_SEL | FALSE |
| DYN_IDIV_SEL | FALSE |
| DYN_LPF_SEL | FALSE |
| DYN_MDIV_SEL | FALSE |
| DYN_ODIV0_SEL | FALSE |
| DYN_ODIV1_SEL | FALSE |
| DYN_ODIV2_SEL | FALSE |
| DYN_ODIV3_SEL | FALSE |
| DYN_ODIV4_SEL | FALSE |
| DYN_ODIV5_SEL | FALSE |
| DYN_ODIV6_SEL | FALSE |
| DYN_PE0_SEL | FALSE |
| DYN_PE1_SEL | FALSE |
| DYN_PE2_SEL | FALSE |
| DYN_PE3_SEL | FALSE |
| DYN_PE4_SEL | FALSE |
| DYN_PE5_SEL | FALSE |
| DYN_PE6_SEL | FALSE |
| FBDIV_SEL | 1 (0b00000000000000000000000000000001) |
| FCLKIN | 100.0 |
| ICP_SEL | xxxxxx |
| IDIV_SEL | 1 (0b00000000000000000000000000000001) |
| LPF_CAP | 0 (0b00) |
| LPF_RES | xxx |
| MDIV_FRAC_SEL | 0 (0b00000000000000000000000000000000) |
| MDIV_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV0_FRAC_SEL | 0 (0b00000000000000000000000000000000) |
| ODIV0_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV1_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV2_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV3_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV4_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV5_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV6_SEL | 8 (0b00000000000000000000000000001000) |
| RESET_I_EN | FALSE |
| RESET_O_EN | FALSE |
| SSC_EN | FALSE |
PLL #(
.CLK0_IN_SEL(CLK0_IN_SEL),
.CLK0_OUT_SEL(CLK0_OUT_SEL),
.CLK1_IN_SEL(CLK1_IN_SEL),
.CLK1_OUT_SEL(CLK1_OUT_SEL),
.CLK2_IN_SEL(CLK2_IN_SEL),
.CLK2_OUT_SEL(CLK2_OUT_SEL),
.CLK3_IN_SEL(CLK3_IN_SEL),
.CLK3_OUT_SEL(CLK3_OUT_SEL),
.CLK4_IN_SEL(CLK4_IN_SEL),
.CLK4_OUT_SEL(CLK4_OUT_SEL),
.CLK5_IN_SEL(CLK5_IN_SEL),
.CLK5_OUT_SEL(CLK5_OUT_SEL),
.CLK6_IN_SEL(CLK6_IN_SEL),
.CLK6_OUT_SEL(CLK6_OUT_SEL),
.CLKFB_SEL(CLKFB_SEL),
.CLKOUT0_DT_DIR(CLKOUT0_DT_DIR),
.CLKOUT0_DT_STEP(CLKOUT0_DT_STEP),
.CLKOUT0_EN(CLKOUT0_EN),
.CLKOUT0_PE_COARSE(CLKOUT0_PE_COARSE),
.CLKOUT0_PE_FINE(CLKOUT0_PE_FINE),
.CLKOUT1_DT_DIR(CLKOUT1_DT_DIR),
.CLKOUT1_DT_STEP(CLKOUT1_DT_STEP),
.CLKOUT1_EN(CLKOUT1_EN),
.CLKOUT1_PE_COARSE(CLKOUT1_PE_COARSE),
.CLKOUT1_PE_FINE(CLKOUT1_PE_FINE),
.CLKOUT2_DT_DIR(CLKOUT2_DT_DIR),
.CLKOUT2_DT_STEP(CLKOUT2_DT_STEP),
.CLKOUT2_EN(CLKOUT2_EN),
.CLKOUT2_PE_COARSE(CLKOUT2_PE_COARSE),
.CLKOUT2_PE_FINE(CLKOUT2_PE_FINE),
.CLKOUT3_DT_DIR(CLKOUT3_DT_DIR),
.CLKOUT3_DT_STEP(CLKOUT3_DT_STEP),
.CLKOUT3_EN(CLKOUT3_EN),
.CLKOUT3_PE_COARSE(CLKOUT3_PE_COARSE),
.CLKOUT3_PE_FINE(CLKOUT3_PE_FINE),
.CLKOUT4_EN(CLKOUT4_EN),
.CLKOUT4_PE_COARSE(CLKOUT4_PE_COARSE),
.CLKOUT4_PE_FINE(CLKOUT4_PE_FINE),
.CLKOUT5_EN(CLKOUT5_EN),
.CLKOUT5_PE_COARSE(CLKOUT5_PE_COARSE),
.CLKOUT5_PE_FINE(CLKOUT5_PE_FINE),
.CLKOUT6_EN(CLKOUT6_EN),
.CLKOUT6_PE_COARSE(CLKOUT6_PE_COARSE),
.CLKOUT6_PE_FINE(CLKOUT6_PE_FINE),
.DE0_EN(DE0_EN),
.DE1_EN(DE1_EN),
.DE2_EN(DE2_EN),
.DE3_EN(DE3_EN),
.DE4_EN(DE4_EN),
.DE5_EN(DE5_EN),
.DE6_EN(DE6_EN),
.DYN_DPA_EN(DYN_DPA_EN),
.DYN_DT0_SEL(DYN_DT0_SEL),
.DYN_DT1_SEL(DYN_DT1_SEL),
.DYN_DT2_SEL(DYN_DT2_SEL),
.DYN_DT3_SEL(DYN_DT3_SEL),
.DYN_FBDIV_SEL(DYN_FBDIV_SEL),
.DYN_ICP_SEL(DYN_ICP_SEL),
.DYN_IDIV_SEL(DYN_IDIV_SEL),
.DYN_LPF_SEL(DYN_LPF_SEL),
.DYN_MDIV_SEL(DYN_MDIV_SEL),
.DYN_ODIV0_SEL(DYN_ODIV0_SEL),
.DYN_ODIV1_SEL(DYN_ODIV1_SEL),
.DYN_ODIV2_SEL(DYN_ODIV2_SEL),
.DYN_ODIV3_SEL(DYN_ODIV3_SEL),
.DYN_ODIV4_SEL(DYN_ODIV4_SEL),
.DYN_ODIV5_SEL(DYN_ODIV5_SEL),
.DYN_ODIV6_SEL(DYN_ODIV6_SEL),
.DYN_PE0_SEL(DYN_PE0_SEL),
.DYN_PE1_SEL(DYN_PE1_SEL),
.DYN_PE2_SEL(DYN_PE2_SEL),
.DYN_PE3_SEL(DYN_PE3_SEL),
.DYN_PE4_SEL(DYN_PE4_SEL),
.DYN_PE5_SEL(DYN_PE5_SEL),
.DYN_PE6_SEL(DYN_PE6_SEL),
.FBDIV_SEL(FBDIV_SEL),
.FCLKIN(FCLKIN),
.ICP_SEL(ICP_SEL),
.IDIV_SEL(IDIV_SEL),
.LPF_CAP(LPF_CAP),
.LPF_RES(LPF_RES),
.MDIV_FRAC_SEL(MDIV_FRAC_SEL),
.MDIV_SEL(MDIV_SEL),
.ODIV0_FRAC_SEL(ODIV0_FRAC_SEL),
.ODIV0_SEL(ODIV0_SEL),
.ODIV1_SEL(ODIV1_SEL),
.ODIV2_SEL(ODIV2_SEL),
.ODIV3_SEL(ODIV3_SEL),
.ODIV4_SEL(ODIV4_SEL),
.ODIV5_SEL(ODIV5_SEL),
.ODIV6_SEL(ODIV6_SEL),
.RESET_I_EN(RESET_I_EN),
.RESET_O_EN(RESET_O_EN),
.SSC_EN(SSC_EN)
) pll_inst (
.CLKFB(CLKFB),
.CLKFBOUT(CLKFBOUT),
.CLKIN(CLKIN),
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.CLKOUT6(CLKOUT6),
.DT0(DT0),
.DT1(DT1),
.DT2(DT2),
.DT3(DT3),
.ENCLK0(ENCLK0),
.ENCLK1(ENCLK1),
.ENCLK2(ENCLK2),
.ENCLK3(ENCLK3),
.ENCLK4(ENCLK4),
.ENCLK5(ENCLK5),
.ENCLK6(ENCLK6),
.FBDSEL(FBDSEL),
.ICPSEL(ICPSEL),
.IDSEL(IDSEL),
.LOCK(LOCK),
.LPFCAP(LPFCAP),
.LPFRES(LPFRES),
.MDSEL(MDSEL),
.MDSEL_FRAC(MDSEL_FRAC),
.ODSEL0(ODSEL0),
.ODSEL0_FRAC(ODSEL0_FRAC),
.ODSEL1(ODSEL1),
.ODSEL2(ODSEL2),
.ODSEL3(ODSEL3),
.ODSEL4(ODSEL4),
.ODSEL5(ODSEL5),
.ODSEL6(ODSEL6),
.PLLPWD(PLLPWD),
.PSDIR(PSDIR),
.PSPULSE(PSPULSE),
.PSSEL(PSSEL),
.RESET(RESET),
.RESET_I(RESET_I),
.RESET_O(RESET_O),
.SSCMDSEL(SSCMDSEL),
.SSCMDSEL_FRAC(SSCMDSEL_FRAC),
.SSCON(SSCON),
.SSCPOL(SSCPOL)
);The Gowin PLLA primitive supports independent adjustment of clock frequency, phase, and duty cycle based on a given reference input clock. It provides seven clock outputs.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| CLKFB | 1 | input |
| CLKFBOUT | 1 | output |
| CLKIN | 1 | input |
| CLKOUT0 | 1 | output |
| CLKOUT1 | 1 | output |
| CLKOUT2 | 1 | output |
| CLKOUT3 | 1 | output |
| CLKOUT4 | 1 | output |
| CLKOUT5 | 1 | output |
| CLKOUT6 | 1 | output |
| LOCK | 1 | output |
| MDAINC | 1 | input |
| MDCLK | 1 | input |
| MDOPC | 2 | input |
| MDRDO | 8 | output |
| MDWDI | 8 | input |
| PLLPWD | 1 | input |
| PSDIR | 1 | input |
| PSPULSE | 1 | input |
| PSSEL | 3 | input |
| RESET | 1 | input |
| RESET_I | 1 | input |
| RESET_O | 1 | input |
| SSCMDSEL | 7 | input |
| SSCMDSEL_FRAC | 3 | input |
| SSCON | 1 | input |
| SSCPOL | 1 | input |
| Parameter | Default Value |
|---|---|
| CLK0_IN_SEL | 0 (0b0) |
| CLK0_OUT_SEL | 0 (0b0) |
| CLK1_IN_SEL | 0 (0b0) |
| CLK1_OUT_SEL | 0 (0b0) |
| CLK2_IN_SEL | 0 (0b0) |
| CLK2_OUT_SEL | 0 (0b0) |
| CLK3_IN_SEL | 0 (0b0) |
| CLK3_OUT_SEL | 0 (0b0) |
| CLK4_IN_SEL | 0 (0b00) |
| CLK4_OUT_SEL | 0 (0b0) |
| CLK5_IN_SEL | 0 (0b0) |
| CLK5_OUT_SEL | 0 (0b0) |
| CLK6_IN_SEL | 0 (0b0) |
| CLK6_OUT_SEL | 0 (0b0) |
| CLKFB_SEL | INTERNAL |
| CLKOUT0_DT_DIR | 1 (0b1) |
| CLKOUT0_DT_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUT0_EN | TRUE |
| CLKOUT0_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT0_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT1_DT_DIR | 1 (0b1) |
| CLKOUT1_DT_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUT1_EN | FALSE |
| CLKOUT1_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT1_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT2_DT_DIR | 1 (0b1) |
| CLKOUT2_DT_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUT2_EN | FALSE |
| CLKOUT2_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT2_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT3_DT_DIR | 1 (0b1) |
| CLKOUT3_DT_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUT3_EN | FALSE |
| CLKOUT3_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT3_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT4_EN | FALSE |
| CLKOUT4_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT4_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT5_EN | FALSE |
| CLKOUT5_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT5_PE_FINE | 0 (0b00000000000000000000000000000000) |
| CLKOUT6_EN | FALSE |
| CLKOUT6_PE_COARSE | 0 (0b00000000000000000000000000000000) |
| CLKOUT6_PE_FINE | 0 (0b00000000000000000000000000000000) |
| DE0_EN | FALSE |
| DE1_EN | FALSE |
| DE2_EN | FALSE |
| DE3_EN | FALSE |
| DE4_EN | FALSE |
| DE5_EN | FALSE |
| DE6_EN | FALSE |
| DYN_DPA_EN | FALSE |
| DYN_PE0_SEL | FALSE |
| DYN_PE1_SEL | FALSE |
| DYN_PE2_SEL | FALSE |
| DYN_PE3_SEL | FALSE |
| DYN_PE4_SEL | FALSE |
| DYN_PE5_SEL | FALSE |
| DYN_PE6_SEL | FALSE |
| FBDIV_SEL | 1 (0b00000000000000000000000000000001) |
| FCLKIN | 100.0 |
| ICP_SEL | xxxxxx |
| IDIV_SEL | 1 (0b00000000000000000000000000000001) |
| LPF_CAP | 0 (0b00) |
| LPF_RES | xxx |
| MDIV_FRAC_SEL | 0 (0b00000000000000000000000000000000) |
| MDIV_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV0_FRAC_SEL | 0 (0b00000000000000000000000000000000) |
| ODIV0_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV1_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV2_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV3_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV4_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV5_SEL | 8 (0b00000000000000000000000000001000) |
| ODIV6_SEL | 8 (0b00000000000000000000000000001000) |
| RESET_I_EN | FALSE |
| RESET_O_EN | FALSE |
| SSC_EN | FALSE |
PLLA #(
.CLK0_IN_SEL(CLK0_IN_SEL),
.CLK0_OUT_SEL(CLK0_OUT_SEL),
.CLK1_IN_SEL(CLK1_IN_SEL),
.CLK1_OUT_SEL(CLK1_OUT_SEL),
.CLK2_IN_SEL(CLK2_IN_SEL),
.CLK2_OUT_SEL(CLK2_OUT_SEL),
.CLK3_IN_SEL(CLK3_IN_SEL),
.CLK3_OUT_SEL(CLK3_OUT_SEL),
.CLK4_IN_SEL(CLK4_IN_SEL),
.CLK4_OUT_SEL(CLK4_OUT_SEL),
.CLK5_IN_SEL(CLK5_IN_SEL),
.CLK5_OUT_SEL(CLK5_OUT_SEL),
.CLK6_IN_SEL(CLK6_IN_SEL),
.CLK6_OUT_SEL(CLK6_OUT_SEL),
.CLKFB_SEL(CLKFB_SEL),
.CLKOUT0_DT_DIR(CLKOUT0_DT_DIR),
.CLKOUT0_DT_STEP(CLKOUT0_DT_STEP),
.CLKOUT0_EN(CLKOUT0_EN),
.CLKOUT0_PE_COARSE(CLKOUT0_PE_COARSE),
.CLKOUT0_PE_FINE(CLKOUT0_PE_FINE),
.CLKOUT1_DT_DIR(CLKOUT1_DT_DIR),
.CLKOUT1_DT_STEP(CLKOUT1_DT_STEP),
.CLKOUT1_EN(CLKOUT1_EN),
.CLKOUT1_PE_COARSE(CLKOUT1_PE_COARSE),
.CLKOUT1_PE_FINE(CLKOUT1_PE_FINE),
.CLKOUT2_DT_DIR(CLKOUT2_DT_DIR),
.CLKOUT2_DT_STEP(CLKOUT2_DT_STEP),
.CLKOUT2_EN(CLKOUT2_EN),
.CLKOUT2_PE_COARSE(CLKOUT2_PE_COARSE),
.CLKOUT2_PE_FINE(CLKOUT2_PE_FINE),
.CLKOUT3_DT_DIR(CLKOUT3_DT_DIR),
.CLKOUT3_DT_STEP(CLKOUT3_DT_STEP),
.CLKOUT3_EN(CLKOUT3_EN),
.CLKOUT3_PE_COARSE(CLKOUT3_PE_COARSE),
.CLKOUT3_PE_FINE(CLKOUT3_PE_FINE),
.CLKOUT4_EN(CLKOUT4_EN),
.CLKOUT4_PE_COARSE(CLKOUT4_PE_COARSE),
.CLKOUT4_PE_FINE(CLKOUT4_PE_FINE),
.CLKOUT5_EN(CLKOUT5_EN),
.CLKOUT5_PE_COARSE(CLKOUT5_PE_COARSE),
.CLKOUT5_PE_FINE(CLKOUT5_PE_FINE),
.CLKOUT6_EN(CLKOUT6_EN),
.CLKOUT6_PE_COARSE(CLKOUT6_PE_COARSE),
.CLKOUT6_PE_FINE(CLKOUT6_PE_FINE),
.DE0_EN(DE0_EN),
.DE1_EN(DE1_EN),
.DE2_EN(DE2_EN),
.DE3_EN(DE3_EN),
.DE4_EN(DE4_EN),
.DE5_EN(DE5_EN),
.DE6_EN(DE6_EN),
.DYN_DPA_EN(DYN_DPA_EN),
.DYN_PE0_SEL(DYN_PE0_SEL),
.DYN_PE1_SEL(DYN_PE1_SEL),
.DYN_PE2_SEL(DYN_PE2_SEL),
.DYN_PE3_SEL(DYN_PE3_SEL),
.DYN_PE4_SEL(DYN_PE4_SEL),
.DYN_PE5_SEL(DYN_PE5_SEL),
.DYN_PE6_SEL(DYN_PE6_SEL),
.FBDIV_SEL(FBDIV_SEL),
.FCLKIN(FCLKIN),
.ICP_SEL(ICP_SEL),
.IDIV_SEL(IDIV_SEL),
.LPF_CAP(LPF_CAP),
.LPF_RES(LPF_RES),
.MDIV_FRAC_SEL(MDIV_FRAC_SEL),
.MDIV_SEL(MDIV_SEL),
.ODIV0_FRAC_SEL(ODIV0_FRAC_SEL),
.ODIV0_SEL(ODIV0_SEL),
.ODIV1_SEL(ODIV1_SEL),
.ODIV2_SEL(ODIV2_SEL),
.ODIV3_SEL(ODIV3_SEL),
.ODIV4_SEL(ODIV4_SEL),
.ODIV5_SEL(ODIV5_SEL),
.ODIV6_SEL(ODIV6_SEL),
.RESET_I_EN(RESET_I_EN),
.RESET_O_EN(RESET_O_EN),
.SSC_EN(SSC_EN)
) plla_inst (
.CLKFB(CLKFB),
.CLKFBOUT(CLKFBOUT),
.CLKIN(CLKIN),
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.CLKOUT6(CLKOUT6),
.LOCK(LOCK),
.MDAINC(MDAINC),
.MDCLK(MDCLK),
.MDOPC(MDOPC),
.MDRDO(MDRDO),
.MDWDI(MDWDI),
.PLLPWD(PLLPWD),
.PSDIR(PSDIR),
.PSPULSE(PSPULSE),
.PSSEL(PSSEL),
.RESET(RESET),
.RESET_I(RESET_I),
.RESET_O(RESET_O),
.SSCMDSEL(SSCMDSEL),
.SSCMDSEL_FRAC(SSCMDSEL_FRAC),
.SSCON(SSCON),
.SSCPOL(SSCPOL)
);The Gowin PLL (Phase-Locked Loop) primitive, denoted as "PLLO", supports four clock outputs and adjusts frequency, phase, and duty cycle based on a given input clock. It can adjust the frequency of the input clock CLKIN through multiplication and division.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| CLKFB | 1 | input |
| CLKIN | 1 | input |
| CLKOUTA | 1 | output |
| CLKOUTB | 1 | output |
| CLKOUTC | 1 | output |
| CLKOUTD | 1 | output |
| DTA | 4 | input |
| DTB | 4 | input |
| ENCLKA | 1 | input |
| ENCLKB | 1 | input |
| ENCLKC | 1 | input |
| ENCLKD | 1 | input |
| FBDSEL | 6 | input |
| ICPSEL | 5 | input |
| IDSEL | 6 | input |
| LOCK | 1 | output |
| LPFRES | 3 | input |
| ODSELA | 7 | input |
| ODSELB | 7 | input |
| ODSELC | 7 | input |
| ODSELD | 7 | input |
| PSDIR | 1 | input |
| PSPULSE | 1 | input |
| PSSEL | 2 | input |
| RESET | 1 | input |
| RESET_I | 1 | input |
| RESET_P | 1 | input |
| RESET_S | 1 | input |
| Parameter | Default Value |
|---|---|
| CLKA_IN_SEL | 0 (0b00) |
| CLKA_OUT_SEL | 0 (0b0) |
| CLKB_IN_SEL | 0 (0b00) |
| CLKB_OUT_SEL | 0 (0b0) |
| CLKC_IN_SEL | 0 (0b00) |
| CLKC_OUT_SEL | 0 (0b0) |
| CLKD_IN_SEL | 0 (0b00) |
| CLKD_OUT_SEL | 0 (0b0) |
| CLKFB_SEL | INTERNAL |
| CLKOUTA_DT_DIR | 1 (0b1) |
| CLKOUTA_DT_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUTA_EN | TRUE |
| CLKOUTB_DT_DIR | 1 (0b1) |
| CLKOUTB_DT_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUTB_EN | TRUE |
| CLKOUTC_EN | TRUE |
| CLKOUTD_EN | TRUE |
| DTMS_ENB | FALSE |
| DTMS_ENC | FALSE |
| DTMS_END | FALSE |
| DYN_DPA_EN | FALSE |
| DYN_DTA_SEL | FALSE |
| DYN_DTB_SEL | FALSE |
| DYN_FBDIV_SEL | FALSE |
| DYN_ICP_SEL | FALSE |
| DYN_IDIV_SEL | FALSE |
| DYN_ODIVA_SEL | FALSE |
| DYN_ODIVB_SEL | FALSE |
| DYN_ODIVC_SEL | FALSE |
| DYN_ODIVD_SEL | FALSE |
| DYN_PSB_SEL | FALSE |
| DYN_PSC_SEL | FALSE |
| DYN_PSD_SEL | FALSE |
| DYN_RES_SEL | FALSE |
| FBDIV_SEL | 0 (0b00000000000000000000000000000000) |
| FCLKIN | 100.0 |
| ICP_SEL | xxxxx |
| IDIV_SEL | 0 (0b00000000000000000000000000000000) |
| LPR_REF | xxxxxxx |
| ODIVA_SEL | 6 (0b00000000000000000000000000000110) |
| ODIVB_SEL | 6 (0b00000000000000000000000000000110) |
| ODIVC_SEL | 6 (0b00000000000000000000000000000110) |
| ODIVD_SEL | 6 (0b00000000000000000000000000000110) |
| PSB_COARSE | 1 (0b00000000000000000000000000000001) |
| PSB_FINE | 0 (0b00000000000000000000000000000000) |
| PSC_COARSE | 1 (0b00000000000000000000000000000001) |
| PSC_FINE | 0 (0b00000000000000000000000000000000) |
| PSD_COARSE | 1 (0b00000000000000000000000000000001) |
| PSD_FINE | 0 (0b00000000000000000000000000000000) |
| RESET_I_EN | FALSE |
| RESET_S_EN | FALSE |
PLLO #(
.CLKA_IN_SEL(CLKA_IN_SEL),
.CLKA_OUT_SEL(CLKA_OUT_SEL),
.CLKB_IN_SEL(CLKB_IN_SEL),
.CLKB_OUT_SEL(CLKB_OUT_SEL),
.CLKC_IN_SEL(CLKC_IN_SEL),
.CLKC_OUT_SEL(CLKC_OUT_SEL),
.CLKD_IN_SEL(CLKD_IN_SEL),
.CLKD_OUT_SEL(CLKD_OUT_SEL),
.CLKFB_SEL(CLKFB_SEL),
.CLKOUTA_DT_DIR(CLKOUTA_DT_DIR),
.CLKOUTA_DT_STEP(CLKOUTA_DT_STEP),
.CLKOUTA_EN(CLKOUTA_EN),
.CLKOUTB_DT_DIR(CLKOUTB_DT_DIR),
.CLKOUTB_DT_STEP(CLKOUTB_DT_STEP),
.CLKOUTB_EN(CLKOUTB_EN),
.CLKOUTC_EN(CLKOUTC_EN),
.CLKOUTD_EN(CLKOUTD_EN),
.DTMS_ENB(DTMS_ENB),
.DTMS_ENC(DTMS_ENC),
.DTMS_END(DTMS_END),
.DYN_DPA_EN(DYN_DPA_EN),
.DYN_DTA_SEL(DYN_DTA_SEL),
.DYN_DTB_SEL(DYN_DTB_SEL),
.DYN_FBDIV_SEL(DYN_FBDIV_SEL),
.DYN_ICP_SEL(DYN_ICP_SEL),
.DYN_IDIV_SEL(DYN_IDIV_SEL),
.DYN_ODIVA_SEL(DYN_ODIVA_SEL),
.DYN_ODIVB_SEL(DYN_ODIVB_SEL),
.DYN_ODIVC_SEL(DYN_ODIVC_SEL),
.DYN_ODIVD_SEL(DYN_ODIVD_SEL),
.DYN_PSB_SEL(DYN_PSB_SEL),
.DYN_PSC_SEL(DYN_PSC_SEL),
.DYN_PSD_SEL(DYN_PSD_SEL),
.DYN_RES_SEL(DYN_RES_SEL),
.FBDIV_SEL(FBDIV_SEL),
.FCLKIN(FCLKIN),
.ICP_SEL(ICP_SEL),
.IDIV_SEL(IDIV_SEL),
.LPR_REF(LPR_REF),
.ODIVA_SEL(ODIVA_SEL),
.ODIVB_SEL(ODIVB_SEL),
.ODIVC_SEL(ODIVC_SEL),
.ODIVD_SEL(ODIVD_SEL),
.PSB_COARSE(PSB_COARSE),
.PSB_FINE(PSB_FINE),
.PSC_COARSE(PSC_COARSE),
.PSC_FINE(PSC_FINE),
.PSD_COARSE(PSD_COARSE),
.PSD_FINE(PSD_FINE),
.RESET_I_EN(RESET_I_EN),
.RESET_S_EN(RESET_S_EN)
) pllo_inst (
.CLKFB(CLKFB),
.CLKIN(CLKIN),
.CLKOUTA(CLKOUTA),
.CLKOUTB(CLKOUTB),
.CLKOUTC(CLKOUTC),
.CLKOUTD(CLKOUTD),
.DTA(DTA),
.DTB(DTB),
.ENCLKA(ENCLKA),
.ENCLKB(ENCLKB),
.ENCLKC(ENCLKC),
.ENCLKD(ENCLKD),
.FBDSEL(FBDSEL),
.ICPSEL(ICPSEL),
.IDSEL(IDSEL),
.LOCK(LOCK),
.LPFRES(LPFRES),
.ODSELA(ODSELA),
.ODSELB(ODSELB),
.ODSELC(ODSELC),
.ODSELD(ODSELD),
.PSDIR(PSDIR),
.PSPULSE(PSPULSE),
.PSSEL(PSSEL),
.RESET(RESET),
.RESET_I(RESET_I),
.RESET_P(RESET_P),
.RESET_S(RESET_S)
);The Gowin PLLVR primitive is a Phase-Locked Loop with regulator that uses an external input reference clock signal to control the frequency and phase in the loop of internal oscillation signals. It can adjust the frequency, phase, duty cycle, and frequency (multiplication and division) of the input clock based on given parameters IDIV, FBDIV, ODIV, and SDIV, which can be adjusted to get the clock signal with expected frequency. The formulas for adjusting the output frequencies are fCLKOUT = (fCLKIN * FBDIV) / IDIV, fVCO = fCLKOUT * ODIV, fCLKOUTD = fCLKOUT * SDIV, and fPFD = fCLKIN / IDIV = fCLKOUT / FBDIV.
This device is supported in Apicula.
| Port | Size | Direction |
|---|---|---|
| CLKFB | 1 | input |
| CLKIN | 1 | input |
| CLKOUT | 1 | output |
| CLKOUTD | 1 | output |
| CLKOUTD3 | 1 | output |
| CLKOUTP | 1 | output |
| DUTYDA | 4 | input |
| FBDSEL | 6 | input |
| FDLY | 4 | input |
| IDSEL | 6 | input |
| LOCK | 1 | output |
| ODSEL | 6 | input |
| PSDA | 4 | input |
| RESET | 1 | input |
| RESET_P | 1 | input |
| VREN | 1 | input |
| Parameter | Default Value |
|---|---|
| CLKFB_SEL | internal |
| CLKOUTD3_SRC | CLKOUT |
| CLKOUTD_BYPASS | false |
| CLKOUTD_SRC | CLKOUT |
| CLKOUTP_BYPASS | false |
| CLKOUTP_DLY_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUTP_FT_DIR | 1 (0b1) |
| CLKOUT_BYPASS | false |
| CLKOUT_DLY_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUT_FT_DIR | 1 (0b1) |
| DEVICE | GW1NS-4 |
| DUTYDA_SEL | 1000 |
| DYN_DA_EN | false |
| DYN_FBDIV_SEL | false |
| DYN_IDIV_SEL | false |
| DYN_ODIV_SEL | false |
| DYN_SDIV_SEL | 2 (0b00000000000000000000000000000010) |
| FBDIV_SEL | 0 (0b00000000000000000000000000000000) |
| FCLKIN | 100.0 |
| IDIV_SEL | 0 (0b00000000000000000000000000000000) |
| ODIV_SEL | 8 (0b00000000000000000000000000001000) |
| PSDA_SEL | 0000 |
PLLVR #(
.CLKFB_SEL(CLKFB_SEL),
.CLKOUTD3_SRC(CLKOUTD3_SRC),
.CLKOUTD_BYPASS(CLKOUTD_BYPASS),
.CLKOUTD_SRC(CLKOUTD_SRC),
.CLKOUTP_BYPASS(CLKOUTP_BYPASS),
.CLKOUTP_DLY_STEP(CLKOUTP_DLY_STEP),
.CLKOUTP_FT_DIR(CLKOUTP_FT_DIR),
.CLKOUT_BYPASS(CLKOUT_BYPASS),
.CLKOUT_DLY_STEP(CLKOUT_DLY_STEP),
.CLKOUT_FT_DIR(CLKOUT_FT_DIR),
.DEVICE(DEVICE),
.DUTYDA_SEL(DUTYDA_SEL),
.DYN_DA_EN(DYN_DA_EN),
.DYN_FBDIV_SEL(DYN_FBDIV_SEL),
.DYN_IDIV_SEL(DYN_IDIV_SEL),
.DYN_ODIV_SEL(DYN_ODIV_SEL),
.DYN_SDIV_SEL(DYN_SDIV_SEL),
.FBDIV_SEL(FBDIV_SEL),
.FCLKIN(FCLKIN),
.IDIV_SEL(IDIV_SEL),
.ODIV_SEL(ODIV_SEL),
.PSDA_SEL(PSDA_SEL)
) pllvr_inst (
.CLKFB(CLKFB),
.CLKIN(CLKIN),
.CLKOUT(CLKOUT),
.CLKOUTD(CLKOUTD),
.CLKOUTD3(CLKOUTD3),
.CLKOUTP(CLKOUTP),
.DUTYDA(DUTYDA),
.FBDSEL(FBDSEL),
.FDLY(FDLY),
.IDSEL(IDSEL),
.LOCK(LOCK),
.ODSEL(ODSEL),
.PSDA(PSDA),
.RESET(RESET),
.RESET_P(RESET_P),
.VREN(VREN)
);Here is a summary of the functionality of the Gowin rPLL primitive based on the provided text:
The Gowin rPLL (rational Phase-Locked Loop) primitive adjusts clock phase, duty cycle, frequency (multiplication and division), to generate output clocks with different phases and frequencies. It can multiply or divide the input clock frequency by a factor determined by FBDIV and IDIV, respectively, resulting in an output clock frequency of fCLKOUT = (fCLKIN * FBDIV) / IDIV. Additionally, it can adjust the output clock duty cycle based on the ODIV value, with the output clock frequency being fVCO = fCLKOUT * ODIV.
This device is supported in Apicula.
| Port | Size | Direction |
|---|---|---|
| CLKFB | 1 | input |
| CLKIN | 1 | input |
| CLKOUT | 1 | output |
| CLKOUTD | 1 | output |
| CLKOUTD3 | 1 | output |
| CLKOUTP | 1 | output |
| DUTYDA | 4 | input |
| FBDSEL | 6 | input |
| FDLY | 4 | input |
| IDSEL | 6 | input |
| LOCK | 1 | output |
| ODSEL | 6 | input |
| PSDA | 4 | input |
| RESET | 1 | input |
| RESET_P | 1 | input |
| Parameter | Default Value |
|---|---|
| CLKFB_SEL | internal |
| CLKOUTD3_SRC | CLKOUT |
| CLKOUTD_BYPASS | false |
| CLKOUTD_SRC | CLKOUT |
| CLKOUTP_BYPASS | false |
| CLKOUTP_DLY_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUTP_FT_DIR | 1 (0b1) |
| CLKOUT_BYPASS | false |
| CLKOUT_DLY_STEP | 0 (0b00000000000000000000000000000000) |
| CLKOUT_FT_DIR | 1 (0b1) |
| DEVICE | GW1N-1 |
| DUTYDA_SEL | 1000 |
| DYN_DA_EN | false |
| DYN_FBDIV_SEL | false |
| DYN_IDIV_SEL | false |
| DYN_ODIV_SEL | false |
| DYN_SDIV_SEL | 2 (0b00000000000000000000000000000010) |
| FBDIV_SEL | 0 (0b00000000000000000000000000000000) |
| FCLKIN | 100.0 |
| IDIV_SEL | 0 (0b00000000000000000000000000000000) |
| ODIV_SEL | 8 (0b00000000000000000000000000001000) |
| PSDA_SEL | 0000 |
rPLL #(
.CLKFB_SEL(CLKFB_SEL),
.CLKOUTD3_SRC(CLKOUTD3_SRC),
.CLKOUTD_BYPASS(CLKOUTD_BYPASS),
.CLKOUTD_SRC(CLKOUTD_SRC),
.CLKOUTP_BYPASS(CLKOUTP_BYPASS),
.CLKOUTP_DLY_STEP(CLKOUTP_DLY_STEP),
.CLKOUTP_FT_DIR(CLKOUTP_FT_DIR),
.CLKOUT_BYPASS(CLKOUT_BYPASS),
.CLKOUT_DLY_STEP(CLKOUT_DLY_STEP),
.CLKOUT_FT_DIR(CLKOUT_FT_DIR),
.DEVICE(DEVICE),
.DUTYDA_SEL(DUTYDA_SEL),
.DYN_DA_EN(DYN_DA_EN),
.DYN_FBDIV_SEL(DYN_FBDIV_SEL),
.DYN_IDIV_SEL(DYN_IDIV_SEL),
.DYN_ODIV_SEL(DYN_ODIV_SEL),
.DYN_SDIV_SEL(DYN_SDIV_SEL),
.FBDIV_SEL(FBDIV_SEL),
.FCLKIN(FCLKIN),
.IDIV_SEL(IDIV_SEL),
.ODIV_SEL(ODIV_SEL),
.PSDA_SEL(PSDA_SEL)
) rpll_inst (
.CLKFB(CLKFB),
.CLKIN(CLKIN),
.CLKOUT(CLKOUT),
.CLKOUTD(CLKOUTD),
.CLKOUTD3(CLKOUTD3),
.CLKOUTP(CLKOUTP),
.DUTYDA(DUTYDA),
.FBDSEL(FBDSEL),
.FDLY(FDLY),
.IDSEL(IDSEL),
.LOCK(LOCK),
.ODSEL(ODSEL),
.PSDA(PSDA),
.RESET(RESET),
.RESET_P(RESET_P)
);