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Pepijn de Vos edited this page Nov 19, 2024 · 2 revisions

IDES10

The IDES10 is a 1-to-10 deserializer that takes a single bit serial input (D) and provides a 10-bit parallel output. It realizes a 1:10 serial-parallel conversion, where the data is shifted by one bit per pulse of PCLK, with the CALIB signal allowing adjustment to the sequence of output data. The output signals are Q0 to Q9, with Q9 being equal to Q0 after 10 shifts.

This device is supported in Apicula.

Ports

Port Size Direction
CALIB 1 input
D 1 input
FCLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
Q2 1 output
Q3 1 output
Q4 1 output
Q5 1 output
Q6 1 output
Q7 1 output
Q8 1 output
Q9 1 output
RESET 1 input

Parameters

Parameter Default Value
GSREN false
LSREN true

Verilog Instantiation

IDES10 #(
    .GSREN(GSREN),
    .LSREN(LSREN)
) ides10_inst (
    .CALIB(CALIB),
    .D(D),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .Q2(Q2),
    .Q3(Q3),
    .Q4(Q4),
    .Q5(Q5),
    .Q6(Q6),
    .Q7(Q7),
    .Q8(Q8),
    .Q9(Q9),
    .RESET(RESET)
);

IDES14

The IDES14 primitive is a 1:14 serial-parallel deserializer that converts one bit of serial input data into 14 bits of parallel output data. The output data is provided at the same clock edge as the input, and can be adjusted in sequence using the CALIB signal. After 14 shifts, the output data will be the same as the data before the shift, with each bit being shifted by one position per pulse.

This device is not yet supported in Apicula

Ports

Port Size Direction
CALIB 1 input
D 1 input
FCLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
Q10 1 output
Q11 1 output
Q12 1 output
Q13 1 output
Q2 1 output
Q3 1 output
Q4 1 output
Q5 1 output
Q6 1 output
Q7 1 output
Q8 1 output
Q9 1 output
RESET 1 input

Verilog Instantiation

IDES14 ides14_inst (
    .CALIB(CALIB),
    .D(D),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .Q10(Q10),
    .Q11(Q11),
    .Q12(Q12),
    .Q13(Q13),
    .Q2(Q2),
    .Q3(Q3),
    .Q4(Q4),
    .Q5(Q5),
    .Q6(Q6),
    .Q7(Q7),
    .Q8(Q8),
    .Q9(Q9),
    .RESET(RESET)
);

IDES16

The Gowin IDES16 primitive is a deserializer that converts 1 bit serial input into 16 bits parallel output, providing data to FPGA logic at the same clock edge. It supports calibration (CALIB) to adjust the sequence of output data, shifting each pulse data by one bit. After 16 shifts, the output data is identical to the original data before the shift. The IDES16 primitive can be used with various Gowin devices and requires a clock signal that is an 18th frequency division of FCLK (i.e., PCLK = FCLK/18).

This device is supported in Apicula.

Ports

Port Size Direction
CALIB 1 input
D 1 input
FCLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
Q10 1 output
Q11 1 output
Q12 1 output
Q13 1 output
Q14 1 output
Q15 1 output
Q2 1 output
Q3 1 output
Q4 1 output
Q5 1 output
Q6 1 output
Q7 1 output
Q8 1 output
Q9 1 output
RESET 1 input

Parameters

Parameter Default Value
GSREN false
LSREN true

Verilog Instantiation

IDES16 #(
    .GSREN(GSREN),
    .LSREN(LSREN)
) ides16_inst (
    .CALIB(CALIB),
    .D(D),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .Q10(Q10),
    .Q11(Q11),
    .Q12(Q12),
    .Q13(Q13),
    .Q14(Q14),
    .Q15(Q15),
    .Q2(Q2),
    .Q3(Q3),
    .Q4(Q4),
    .Q5(Q5),
    .Q6(Q6),
    .Q7(Q7),
    .Q8(Q8),
    .Q9(Q9),
    .RESET(RESET)
);

IDES32

The Gowin IDES32 primitive is a 1-to-32 deserializer that converts 1 bit of serial input into 32 bits of parallel output. The output data is updated at the same clock edge as the input, and the CALIB signal allows for adjustment of the sequence of output data. The data is shifted one bit per pulse, resulting in a 32-bit output after 32 shifts, with the final output being the same as the original 1-bit input.

This device is not yet supported in Apicula

Ports

Port Size Direction
CALIB 1 input
D 1 input
FCLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
Q10 1 output
Q11 1 output
Q12 1 output
Q13 1 output
Q14 1 output
Q15 1 output
Q16 1 output
Q17 1 output
Q18 1 output
Q19 1 output
Q2 1 output
Q20 1 output
Q21 1 output
Q22 1 output
Q23 1 output
Q24 1 output
Q25 1 output
Q26 1 output
Q27 1 output
Q28 1 output
Q29 1 output
Q3 1 output
Q30 1 output
Q31 1 output
Q4 1 output
Q5 1 output
Q6 1 output
Q7 1 output
Q8 1 output
Q9 1 output
RESET 1 input

Verilog Instantiation

IDES32 ides32_inst (
    .CALIB(CALIB),
    .D(D),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .Q10(Q10),
    .Q11(Q11),
    .Q12(Q12),
    .Q13(Q13),
    .Q14(Q14),
    .Q15(Q15),
    .Q16(Q16),
    .Q17(Q17),
    .Q18(Q18),
    .Q19(Q19),
    .Q2(Q2),
    .Q20(Q20),
    .Q21(Q21),
    .Q22(Q22),
    .Q23(Q23),
    .Q24(Q24),
    .Q25(Q25),
    .Q26(Q26),
    .Q27(Q27),
    .Q28(Q28),
    .Q29(Q29),
    .Q3(Q3),
    .Q30(Q30),
    .Q31(Q31),
    .Q4(Q4),
    .Q5(Q5),
    .Q6(Q6),
    .Q7(Q7),
    .Q8(Q8),
    .Q9(Q9),
    .RESET(RESET)
);

IDES4

The Gowin IDES4 primitive is a 1-to-4 deserializer that takes a 1-bit serial input and produces a 4-bit parallel output. It realizes 1:4 serial parallel conversion, where the data is shifted by one bit per pulse, and the output data can be adjusted in sequence using the CALIB signal. The IDES4 primitive supports CALIB to adjust the sequence of output data and provides data output to FPGA logic at the same clock edge.

This device is supported in Apicula.

Ports

Port Size Direction
CALIB 1 input
D 1 input
FCLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
Q2 1 output
Q3 1 output
RESET 1 input

Parameters

Parameter Default Value
GSREN false
LSREN true

Verilog Instantiation

IDES4 #(
    .GSREN(GSREN),
    .LSREN(LSREN)
) ides4_inst (
    .CALIB(CALIB),
    .D(D),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .Q2(Q2),
    .Q3(Q3),
    .RESET(RESET)
);

IDES4_MEM

The IDES4_MEM primitive realizes 1:4 serial-parallel conversion with memory. It takes in data from a serializer at the rising edge of ICLK, and outputs four parallel bits (Q0, Q1, Q2, and Q3) to the FPGA logic at the same clock edge. The output data is provided after shifting each pulse data by one bit, resulting in the original data being restored after four shifts. The primitive also supports CALIB to adjust the sequence of output data and determines phase relationships between PCLK, FCLK, and ICLK based on a DLLSTEP value from DQS.

This device is not yet supported in Apicula

Ports

Port Size Direction
CALIB 1 input
D 1 input
FCLK 1 input
ICLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
Q2 1 output
Q3 1 output
RADDR 3 input
RESET 1 input
WADDR 3 input

Parameters

Parameter Default Value
GSREN
ID
LSREN

Verilog Instantiation

IDES4_MEM #(
    .GSREN(GSREN),
    .ID(ID),
    .LSREN(LSREN)
) ides4_mem_inst (
    .CALIB(CALIB),
    .D(D),
    .FCLK(FCLK),
    .ICLK(ICLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .Q2(Q2),
    .Q3(Q3),
    .RADDR(RADDR),
    .RESET(RESET),
    .WADDR(WADDR)
);

IDES8

The 1-to-8 Deserializer (IDES8) primitive is a deserializer that converts 1 bit of serial input into 8 bits of parallel output. It provides output data at the same clock edge as the input and supports CALIB to adjust the sequence of output data, which is shifted by one bit per pulse. After four shifts, the output data will be the same as before the shift. The primary clock (PCLK) is typically obtained by dividing the high-speed clock (FCLK) frequency by 14.

This device is supported in Apicula.

Ports

Port Size Direction
CALIB 1 input
D 1 input
FCLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
Q2 1 output
Q3 1 output
Q4 1 output
Q5 1 output
Q6 1 output
Q7 1 output
RESET 1 input

Parameters

Parameter Default Value
GSREN false
LSREN true

Verilog Instantiation

IDES8 #(
    .GSREN(GSREN),
    .LSREN(LSREN)
) ides8_inst (
    .CALIB(CALIB),
    .D(D),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .Q2(Q2),
    .Q3(Q3),
    .Q4(Q4),
    .Q5(Q5),
    .Q6(Q6),
    .Q7(Q7),
    .RESET(RESET)
);

IDES8_MEM

The 1:8 Deserializer with Memory (IDES8_MEM) primitive realizes 1:8 serial parallel conversion, providing output data to FPGA logic at the same clock edge. It also supports CALIB (calibration) to adjust the sequence of output data, shifting the data by one bit per pulse and returning to the original state after eight shifts.

This device is not yet supported in Apicula

Ports

Port Size Direction
CALIB 1 input
D 1 input
FCLK 1 input
ICLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
Q2 1 output
Q3 1 output
Q4 1 output
Q5 1 output
Q6 1 output
Q7 1 output
RADDR 3 input
RESET 1 input
WADDR 3 input

Verilog Instantiation

IDES8_MEM ides8_mem_inst (
    .CALIB(CALIB),
    .D(D),
    .FCLK(FCLK),
    .ICLK(ICLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .Q2(Q2),
    .Q3(Q3),
    .Q4(Q4),
    .Q5(Q5),
    .Q6(Q6),
    .Q7(Q7),
    .RADDR(RADDR),
    .RESET(RESET),
    .WADDR(WADDR)
);
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