INV

The Gowin INV primitive is an inverter, which takes a single input signal (I) and produces its inverted output (O). The I/O ports are described as follows: I - Input INV data input; O - Output INV data output. In Verilog, the primitive can be instantiated with the code "INV uut (.O(O), .I(I));" while in VHDL, it is implemented as a component "COMPONENT INV ... PORT ( O:OUTPUT std_logic; I:IN std_logic );".

This device is not yet supported in Apicula

Ports

Port	Size	Direction
I	1	input
O	1	output

Verilog Instantiation

INV inv_inst (
    .I(I),
    .O(O)
);