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Jonathan Neuschäfer edited this page Nov 1, 2022 · 5 revisions

The WPCM450 has six I2C controllers.

device MMIO IRQ GEN bit
SMB0 0xb8006000 26 26
SMB1 0xb8006100 26 27
SMB2 0xb8006200 26 30
SMB3 0xb8006300 23 --
SMB4 0xb8006400 27 --
SMB5 0xb8006500 29 --

The reference clock is the APB clock.

Registers

offset type name description
0x00 u8 SDA serial data register
0x02 u8 ST status register
0x04 u8 CST control/status register
0x06 u8 CTL1 control register 1
0x08 u8 ADDR own address 1
0x0a u8 CTL2 control register 2
0x0c u8 ADDR2 own address 2
0x0e u8 CTL3 control register 3
0x0f u8 alias of CTL3

The NPCM7xx I2C block supports bank switching. This is not the case on WPCM450.

0x0e: CTL3

bit description
1:0 bits 8:7 of frequency divider
2 enable match of SMBus "ARP" address
3 unknown
7:4 always zero

References

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