LPC

The WPCM450 exposes an LPC interface to the host, with two purposes:

• The exchange of IPMI messages via the "keyboard controller style" (KCS) protocol.
• To monitor specific LPC addresses for writes, for example port 0x80 (where BIOS POST codes usually go)

device	MMIO	IRQ	description
KCS	0xb8008000	9	LPC related functions

Interrupts are shared between the two functions.

KCS interface

The KCS interface has three channels of some sort, each of which has a set of registers:

offset (channel 0)	ch 1	ch 2	type	name	description
0x0c	0x1e	0x30	u8	STR	status register
0x0e	0x20	0x32	u8	DOR
0x10	0x22	0x34	u8	DIR
0x10	0x22	0x34	u8	CMR
0x14	0x26	0x38	u8	DOM
0x18	0x2a	0x3c	u8	CTL
0x1a	0x2c	0x3e	u8	IC
0x1c	0x2e	0x40	u8	IE

STR - status register

bit	mask	name	description
0	0x01	OBF
1	0x02	IBF	used as interrupt status flag
2	0x04	F0
3	0x08	CMD
4	0x10	ST0
5	0x20	ST1
6	0x40	ST2
7	0x80	ST3

BIOS POST code monitor

offset	type	name	description
0x42	u8	LADDR	LSB of address
0x44	u8	MADDR	MSB of address
0x46	u8	ENABLE
0x48	u8	STATUS
0x4a	u8	DATA
0x4c	u8	MISC_STATUS

References

• Dell driver for KCS (header)
• Dell driver for bios postcode monitor (header)
• mainline DT binding for LPC KCS device
• OpenBMC DT binding for LPC post code monitor