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GPIOs and pinmux
GPIO pins (numbered 0-127) are organized into eight ports (numbered 0-7). Each pin can be configured to operate as a GPIO or to perform a special function, using the MFSEL registers.
Level- and edge-triggered interrupts ("events") are available for GPIOs 0-15 and 24-25.
The GPIO controller has four interrupt lines. The interrupt-capable GPIOs correspond to the interrupt lines as follows:
| IRQ | GPIOs |
|---|---|
| 2 | GPIO 0-3 |
| 3 | GPIO 4-11 |
| 4 | GPIO 12-15 |
| 5 | GPIO 24-25 |
The Nuvoton NPCM7xx SoCs fundamentally use the same mechanism for pinmuxing (MFSEL registers in GCR), but the GPIO registers have been redesigned, and are now organized in banks. Some pin assignments are the same between WPCM450 and NPCM7xx.
The GPIO controller has the following registers in the
MMIO window at 0xb8003000:
| offset | name | description |
|---|---|---|
| 0x00 | GPEVTYPE | event type |
| 0x04 | GPEVPOL | event polarity |
| 0x08 | GPEVDBNC | event debounce |
| 0x0c | GPEVEN | event enable |
| 0x10 | GPEVST | event status |
Some registers are duplicated per port. Note that GPIOPnPE is in the GCR block.
| port | CFG0 | CFG1 | CFG2 | BLINK | DATAOUT | DATAIN | GPIOPnPE |
|---|---|---|---|---|---|---|---|
| 0 | 0x14 | 0x18 | -- | -- | 0x1c | 0x20 | -- |
| 1 | 0x24 | 0x28 | 0x2c | 0x30 | 0x34 | 0x38 | GCR+0x1c |
| 2 | 0x3c | 0x40 | 0x44 | -- | 0x48 | 0x4c | GCR+0x20 |
| 3 | 0x50 | 0x54 | 0x58 | -- | 0x5c | 0x60 | GCR+0x24 |
| 4 | 0x64 | 0x68 | 0x6c | -- | 0x70 | 0x74 | -- |
| 5 | 0x78 | 0x7c | 0x80 | -- | 0x84 | 0x88 | GCR+0x2c |
| 6 | -- | -- | -- | -- | -- | 0x8c | GCR+0x30 |
| 7 | 0x90 | 0x94 | 0x98 | -- | 0x9c | 0xa0 | GCR+0x34 |
GPEVTYPE determines for each interrupt-capable GPIO, whether it is edge-triggered or level-triggered.
| bit | description |
|---|---|
| 0 | event type of GPIO 0 |
| 1 | event type of GPIO 1 |
| ... | ... |
| 15 | event type of GPIO 15 |
| 16 | event type of GPIO 24 |
| 17 | event type of GPIO 25 |
The following types exist:
| type | description |
|---|---|
| 0 | edge-triggered |
| 1 | level-triggered |
GPEVPOL determines for each interrupt-capable GPIO, whether it is triggered on rising edges / high levels, or falling edges / low levels. It has the same layout as GPEVTYPE.
| polarity | description |
|---|---|
| 0 | falling edge or low level |
| 1 | rising edge or high level |
GPEVDBNC enables/disables debouncing for each interrupt-capable GPIO. Debouncing can only be enabled for GPIO 0-15.
| bit | description |
|---|---|
| 0 | debounce GPIO 0 |
| 1 | debounce GPIO 1 |
| ... | ... |
| 15 | debounce GPIO 15 |
| debounce | description |
|---|---|
| 0 | debounce disabled |
| 1 | debounce enabled |
GPEVEN controls for each interrupt-capable GPIO, whether interrupts are generated. It has the same layout as GPEVTYPE.
| enable | description |
|---|---|
| 0 | event does not generate interrupts |
| 1 | event generates interrupt |
How the 18 events map to the four interrupt lines is described above.
GPEVST tracks the interrupt status of each interrupt-capable GPIO. It has the same layout as GPEVTYPE.
| status | read | write |
|---|---|---|
| 0 | event has not occurred | no action |
| 1 | event has occurred | clear event status |
GPEVST bits are set regardless of GPEVEN.
GPEVST are never cleared automatically, even in level-triggered mode.
This port-specific register determines whether for each pin in a port, whether it is an input or an output.
| bit | description |
|---|---|
| 0 | direction of pin 0 of the port (0=input, 1=output) |
| 1 | direction of pin 1 of the port (0=input, 1=output) |
| ... | ... |
This port-specific register controls automatic blinking. It exists only for port 1.
| bit | description |
|---|---|
| 0:2 | blinking mode of pin 0 |
| 3 | reserved (0) |
| 4:6 | blinking mode of pin 1 |
| 7 | reserved (0) |
| ... | ... |
| 28:30 | blinking mode of pin 7 |
| 31 | reserved (0) |
The following modes exist:
| mode | description |
|---|---|
| 0 | off - use value in DATAOUT |
| 1 | TODO |
| ... | ... |
The blinking patterns of different pins do not run synchronously with each other. When blinking is enabled for a pin, it starts immediate, and at a defined point in the cycle. Thus, by timing register writes carefully, two blinking patterns can be made to run in- or out-of-phase with each other.
This port-specific register determines whether for each pin in a port, whether it is driver low or high when it is in output mode (see CFG0).
| bit | description |
|---|---|
| 0 | output level of pin 0 of the port (0=low, 1=high) |
| 1 | output level of pin 1 of the port (0=low, 1=high) |
| ... | ... |
Bits in DATAOUT can be configured before switching the corresponding pins to output mode. This can be done to avoid glitches.
This port-specific register contains the logic level detected at each pin within a port.
| bit | description |
|---|---|
| 0 | status of pin 0 of the port (0=low, 1=high) |
| 1 | status of pin 1 of the port (0=low, 1=high) |
| ... | ... |
DATAIN reflects the status of a pin even when it is configured as output in CFG0.
Pin multiplexing is configured through the multifunction selection registers MFSEL1 and MFSEL2. See below to see which functions affect which pins.
Note that for most MFSEL bits, 0 selects the GPIO function and 1 selects the special function.
Exceptions to this rule are marked in the columns labeled inv..
| bit | MFSEL1 | inv. | description | MFSEL2 | inv. | description |
|---|---|---|---|---|---|---|
| 0 | SMB3SEL | FI0SEL | fan input 0 | |||
| 1 | SMB4SEL | FI1SEL | fan input 1 | |||
| 2 | SMB5SEL | FI2SEL | fan input 2 | |||
| 3 | SCS1SEL | enable SPI chip select 1 | FI3SEL | fan input 3 | ||
| 4 | SCS2SEL | enable SPI chip select 2 | FI4SEL | fan input 4 | ||
| 5 | SCS3SEL | x | enable SPI chip select 3 | FI5SEL | fan input 5 | |
| 6 | SMB0SEL | FI6SEL | fan input 6 | |||
| 7 | SMB1SEL | FI7SEL | fan input 7 | |||
| 8 | SMB2SEL | FI8SEL | fan input 8 | |||
| 9 | BSPSEL | serial port... | FI9SEL | fan input 9 | ||
| 10 | HSP1SEL | serial port pins 1 | FI10SEL | fan input 10 | ||
| 11 | HSP2SEL | serial port pins 2 | FI11SEL | fan input 11 | ||
| 12 | R1ERRSEL | Ethernet... | FI12SEL | fan input 12 | ||
| 13 | R1MDSEL | Ethernet MAC 1 MDIO | FI13SEL | fan input 13 | ||
| 14 | RMII2SEL | Ethernet... | FI14SEL | fan input 14 | ||
| 15 | R2ERRSEL | Ethernet... | FI15SEL | fan input 15 | ||
| 16 | R2MDSEL | Ethernet... | PWM0SEL | PWM output 0 | ||
| 17 | KBCCSEL | x | PWM1SEL | PWM output 1 | ||
| 18 | DVOSEL[0] | PWM2SEL | PWM output 2 | |||
| 19 | DVOSEL[1] | PWM3SEL | PWM output 3 | |||
| 20 | DVOSEL[2] | PWM4SEL | PWM output 4 | |||
| 21 | CLKOSEL | PWM5SEL | PWM output 5 | |||
| 22 | SMISEL | PWM6SEL | PWM output 6 | |||
| 23 | UINCSEL | something related to USB | PWM7SEL | PWM output 7 | ||
| 24 | GSPISEL | HG0SEL | ||||
| 25 | HG1SEL | |||||
| 26 | MBEN | HG2SEL | ||||
| 27 | related to VCD | HG3SEL | ||||
| 28 | XCS2SEL | HG4SEL | ||||
| 29 | XCS1SEL | HG5SEL | ||||
| 30 | SDIOSEL | HG6SEL | ||||
| 31 | SSPISEL | HG7SEL |
In the following table:
- GPIO# is the GPIO pin number (0-127)
- port is the port number (0-7) as extracted from the Dell driver
- index is the pin number within a port. It is also used as a bit index in port-specific registers
- MFSEL (Z1) indicates the MFSEL register and bit used to configure this pin to a special function or the GPIO function (extracted from Dell)
- MFSEL (Z2) contains the differences in MFSEL configuration from chip version Z2 onward. In the Dell driver, the MFSEL bits indicated in this column are cleared in addition to those indicated in the previous column
| GPIO# | port | index | MFSEL (Z1) | MFSEL (Z2) |
|---|---|---|---|---|
| 0 | 0 | 0 | -- | -- |
| 1 | 0 | 1 | -- | -- |
| 2 | 0 | 2 | -- | -- |
| 3 | 0 | 3 | -- | -- |
| 4 | 0 | 4 | -- | -- |
| 5 | 0 | 5 | -- | -- |
| 6 | 0 | 6 | -- | -- |
| 7 | 0 | 7 | -- | 1.30 SDIOSEL |
| 8 | 0 | 8 | -- | -- |
| 9 | 0 | 9 | -- | -- |
| 10 | 0 | 10 | -- | -- |
| 11 | 0 | 11 | -- | -- |
| 12 | 0 | 12 | 1.24 GSPISEL | 1.31 SSPISEL |
| 13 | 0 | 13 | 1.24 GSPISEL | 1.31 SSPISEL |
| 14 | 0 | 14 | 1.24 GSPISEL | 1.31 SSPISEL |
| 15 | 0 | 15 | 1.24 GSPISEL | 1.31 SSPISEL |
| 16 | 1 | 0 | -- | 2.22 PWM6SEL |
| 17 | 1 | 1 | -- | 2.23 PWM7SEL |
| 18 | 1 | 2 | -- | -- |
| 19 | 1 | 3 | 1.23 UINCSEL | -- |
| 20 | 1 | 4 | 2.24 HG0SEL | 2.20 PWM4SEL |
| 21 | 1 | 5 | 2.25 HG1SEL | 2.21 PWM5SEL |
| 22 | 1 | 6 | 2.26 HG2SEL | 1.30 SDIOSEL |
| 23 | 1 | 7 | 2.27 HG3SEL | -- |
| 24 | 1 | 8 | 2.28 HG4SEL | -- |
| 25 | 1 | 9 | 2.29 HG5SEL | -- |
| 26 | 1 | 10 | 1.2 SMB5SEL | -- |
| 27 | 1 | 11 | 1.2 SMB5SEL | -- |
| 28 | 1 | 12 | 1.1 SMB4SEL | -- |
| 29 | 1 | 13 | 1.1 SMB4SEL | -- |
| 30 | 1 | 14 | 1.0 SMB3SEL | -- |
| 31 | 1 | 15 | 1.0 SMB3SEL | -- |
| 32 | 2 | 0 | 1.3 SCS1SEL | -- |
| 33 | 2 | 1 | 1.4 SCS2SEL | -- |
| 34 | 2 | 2 | 1.5 SCS3SEL | -- |
| 35 | 2 | 3 | 1.29 XCS1SEL | -- |
| 36 | 2 | 4 | 1.28 XCS2SEL | -- |
| 37 | 2 | 5 | 1.18 DVOSEL | -- |
| 38 | 2 | 6 | 1.18 DVOSEL | -- |
| 39 | 2 | 7 | 1.18 DVOSEL | -- |
| 40 | 2 | 8 | 1.18 DVOSEL | -- |
| 41 | 2 | 9 | 1.9 BSPSEL | -- |
| 42 | 2 | 10 | 1.9 BSPSEL | -- |
| 43 | 2 | 11 | 1.10 HSP1SEL | 1.30 SDIOSEL |
| 44 | 2 | 12 | 1.10 HSP1SEL | 1.30 SDIOSEL |
| 45 | 2 | 13 | 1.10 HSP1SEL | 1.30 SDIOSEL |
| 46 | 2 | 14 | 1.10 HSP1SEL | 1.30 SDIOSEL |
| 47 | 2 | 15 | 1.10 HSP1SEL | 1.30 SDIOSEL |
| 48 | 3 | 0 | 1.11 HSP2SEL | -- |
| 49 | 3 | 1 | 1.11 HSP2SEL | -- |
| 50 | 3 | 2 | 1.11 HSP2SEL | -- |
| 51 | 3 | 3 | 1.11 HSP2SEL | -- |
| 52 | 3 | 4 | 1.11 HSP2SEL | -- |
| 53 | 3 | 5 | 1.11 HSP2SEL | -- |
| 54 | 3 | 6 | 1.11 HSP2SEL | -- |
| 55 | 3 | 7 | 1.11 HSP2SEL | -- |
| 56 | 3 | 8 | 1.12 R1ERRSEL | -- |
| 57 | 3 | 9 | 1.13 R1MDSEL | -- |
| 58 | 3 | 10 | 1.13 R1MDSEL | -- |
| 59 | 3 | 11 | 2.30 HG6SEL | -- |
| 60 | 3 | 12 | 2.31 HG7SEL | 1.30 SDIOSEL |
| 61 | 3 | 13 | 1.10 HSP1SEL | -- |
| 62 | 3 | 14 | 1.10 HSP1SEL | -- |
| 63 | 3 | 15 | 1.10 HSP1SEL | -- |
| 64 | 4 | 0 | 2.0 FI0SEL | -- |
| 65 | 4 | 1 | 2.1 FI1SEL | -- |
| 66 | 4 | 2 | 2.2 FI2SEL | -- |
| 67 | 4 | 3 | 2.3 FI3SEL | -- |
| 68 | 4 | 4 | 2.4 FI4SEL | -- |
| 69 | 4 | 5 | 2.5 FI5SEL | -- |
| 70 | 4 | 6 | 2.6 FI6SEL | -- |
| 71 | 4 | 7 | 2.7 FI7SEL | -- |
| 72 | 4 | 8 | 2.8 FI8SEL | -- |
| 73 | 4 | 9 | 2.9 FI9SEL | -- |
| 74 | 4 | 10 | 2.10 FI10SEL | -- |
| 75 | 4 | 11 | 2.11 FI11SEL | -- |
| 76 | 4 | 12 | 2.12 FI12SEL | -- |
| 77 | 4 | 13 | 2.13 FI13SEL | -- |
| 78 | 4 | 14 | 2.14 FI14SEL | -- |
| 79 | 4 | 15 | 2.15 FI15SEL | -- |
| 80 | 5 | 0 | 2.16 PWM0SEL | -- |
| 81 | 5 | 1 | 2.17 PWM1SEL | -- |
| 82 | 5 | 2 | 2.18 PWM2SEL | -- |
| 83 | 5 | 3 | 2.19 PWM3SEL | -- |
| 84 | 5 | 4 | 1.14 RMII2SEL | -- |
| 85 | 5 | 5 | 1.14 RMII2SEL | -- |
| 86 | 5 | 6 | 1.14 RMII2SEL | -- |
| 87 | 5 | 7 | 1.14 RMII2SEL | -- |
| 88 | 5 | 8 | 1.14 RMII2SEL | -- |
| 89 | 5 | 9 | 1.14 RMII2SEL | -- |
| 90 | 5 | 10 | 1.15 R2ERRSEL | -- |
| 91 | 5 | 11 | 1.16 R2MDSEL | -- |
| 92 | 5 | 12 | 1.16 R2MDSEL | -- |
| 93 | 5 | 13 | 1.17 KBCCSEL | -- |
| 94 | 5 | 14 | 1.17 KBCCSEL | -- |
| 95 | 5? | 15 | -- | -- |
| 96 | 6 | 0 | 1.21 CLKOSEL | -- |
| 97 | 6 | 1 | 1.22 SMISEL | -- |
| 98 | 6 | 2 | -- | -- |
| 99 | 6 | 3 | -- | -- |
| 100 | 6 | 4 | -- | -- |
| 101 | 6 | 5 | -- | -- |
| 102 | 6 | 6 | -- | -- |
| 103 | 6 | 7 | -- | -- |
| 104 | 6 | 8 | -- | -- |
| 105 | 6 | 9 | -- | -- |
| 106 | 6 | 10 | -- | -- |
| 107 | 6 | 11 | -- | -- |
| 108 | 6 | 12 | 1.18 DVOSEL | -- |
| 109 | 6 | 13 | 1.18 DVOSEL | -- |
| 110 | 6 | 14 | 1.18 DVOSEL | -- |
| 111 | 6 | 15 | 1.18 DVOSEL | -- |
| 112 | 6! | 16 | 1.18 DVOSEL | -- |
| 113 | 6! | 17 | 1.18 DVOSEL | -- |
| 114 | 7 | 0 | 1.6 SMB0SEL | -- |
| 115 | 7 | 1 | 1.6 SMB0SEL | -- |
| 116 | 7 | 2 | 1.7 SMB1SEL | -- |
| 117 | 7 | 3 | 1.7 SMB1SEL | -- |
| 118 | 7 | 4 | 1.8 SMB2SEL | -- |
| 119 | 7 | 5 | 1.8 SMB2SEL | -- |
| 120 | 7 | 6 | 1.18 DVOSEL | -- |
| 121 | 7 | 7 | 1.18 DVOSEL | -- |
| 122 | 7 | 8 | 1.18 DVOSEL | -- |
| 123 | 7 | 9 | 1.18 DVOSEL | -- |
| 124 | 7 | 10 | 1.18 DVOSEL | -- |
| 125 | 7 | 11 | 1.18 DVOSEL | -- |
| 126 | 7 | 12 | 1.18 DVOSEL | -- |
| 127 | 7 | 13 | 1.18 DVOSEL | -- |
Overview:
Basics:
Peripherals:
- Memory controller
- UART, SPI/SSPI, I2C, SD
- GPIOs and pinmux
- Ethernet
- USB, LPC, PECI, XBUS
- PWM and Tachometer, ADC
- Graphics
Board specifics: