Memory controller

The WPCM450's SDRAM controller connects the chip with DDR-2 memory.

device	MMIO	description
DRAM	0x00000000	DRAM access window
MC	0xb0001000	Memory controller register interface

Part of the DRAM can be used by the GPU, and the CPU can be excluded from writing to this part.

Registers

offset	name	description
0x00	CFG0	Memory control configuration register 0
0x04	CFG1	Memory control configuration register 1
0x08	CFG2	Memory control configuration register 2
0x0c	CFG3	Memory control configuration register 3
0x10	CFG4	Memory control configuration register 4
0x14	CFG5	Memory control configuration register 5
0x18	CFG6	Memory control configuration register 6
0x1c	CFG7	Memory control configuration register 7
0x20	P1_CNT	Port 1 arbitration control register
0x24	P1_ARBT	Port 1 arbitration timer value
0x28	P2_CNT	Port 2 arbitration control register
0x2c	P2_ARBT	Port 2 arbitration timer value
0x30	P3_CNT	Port 3 arbitration control register
0x34	P3_ARBT	Port 3 arbitration timer value
0x38	P4_CNT	Port 4 arbitration control register
0x3c	P4_ARBT	Port 4 arbitration timer value
0x40	P5_CNT	Port 5 arbitration control register
0x44	P5_ARBT	Port 5 arbitration timer value
0x48	P6_CNT	Port 6 arbitration control register
0x4c	P6_ARBT	Port 6 arbitration timer value
0x50	P1_INCRS	Port 1 INCR size control
0x54	P2_INCRS	Port 2 INCR size control
0x58	P3_INCRS	Port 3 INCR size control
0x5c	P4_INCRS	Port 4 INCR size control
0x60	DLL_0	DLL and ODT Configuration Register 0
0x64	DLL_1	PDLL and ODT Configuration Register 1

References

• Register list