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Minor Release v2.45.0

01 Sep 17:32
@ruck314 ruck314
v2.45.0
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Minor Release v2.45.0

Pull Requests Since v2.44.0

Unlabeled

  1. #1101 - adding AxiStreamConcat.vhd
  2. #1102 - _AxiSysMonUltraScale.py Updates
  3. #1110 - AxiStreamConcat.vhd Update
  4. #1106 - Allow custom TDEST and TID on Packetizer output stream
  5. #1103 - python/surf/ethernet/udp/init.py Update
  6. #1104 - Fix 24LC64FT for rogue v6 compatibility
  7. #1105 - Add comments to document PRIORITY_G
  8. #1108 - bug fix for xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd

Pull Request Details

adding AxiStreamConcat.vhd
Author: Larry Ruckman [email protected]
Date: Fri Sep 1 08:32:45 2023 -0700
Pull: #1101 (351 additions, 0 deletions, 1 files changed)
Branch: slaclab/AxiStreamConcat

Notes:

Description

  • AxiStreamConcat.vhd concat multiple AXI stream frames together with no metadata because the frames
    • Assumes the users already knows what the data frame format is
    • Not for general purpose frame combining

_AxiSysMonUltraScale.py Updates
Author: Larry Ruckman [email protected]
Date: Fri Sep 1 10:01:39 2023 -0700
Pull: #1102 (37 additions, 34 deletions, 1 files changed)
Branch: slaclab/VauxpVauxn-array

Notes:

Description

python/surf/ethernet/udp/init.py Update
Author: Larry Ruckman [email protected]
Date: Thu Aug 31 14:27:16 2023 -0700
Pull: #1103 (3 additions, 3 deletions, 1 files changed)
Branch: slaclab/smurf-pcie

Notes:

Description

-bug fix for latest rogue

Fix 24LC64FT for rogue v6 compatibility
Author: Benjamin Reese [email protected]
Date: Fri Sep 1 10:00:35 2023 -0700
Pull: #1104 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/24lc64-fix

Notes:

Description

Add offset param to 24LC64FT I2C PROM chip Rogue Device. Offset is now required by rogue for RemoteVariables.

Add comments to document PRIORITY_G
Author: Benjamin Reese [email protected]
Date: Fri Sep 1 10:00:20 2023 -0700
Pull: #1105 (4 additions, 0 deletions, 1 files changed)
Branch: slaclab/axi-stream-mux-doc

Notes:

Description

Add VHDL comments to document the behavior of PRIORITY_G in AxiStreamMux.

Allow custom TDEST and TID on Packetizer output stream
Author: Benjamin Reese [email protected]
Date: Fri Sep 1 10:00:06 2023 -0700
Pull: #1106 (6 additions, 4 deletions, 2 files changed)
Branch: slaclab/packetizer-feature

Notes:

Description

Generics have been added to allow the TDEST and TID of the packetized output stream to be set to a non-zero value. This is useful if multiple packetizes streams will be later muxed, and you want to assign a custom TDEST or TID to each.

This change should be backward compatible, so TDEST and TID default to zero from the generic.

bug fix for xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd
Author: Larry Ruckman [email protected]
Date: Fri Sep 1 10:01:52 2023 -0700
Pull: #1108 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ClockManagerUltraScale-fix

Notes:

Description

  • Lefthand signal to be exchanged with rigthhand in assignment
  • Confirmed this patch was already applied to xilinx/7Series/general/rtl/ClockManager7.vhd and xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd
  • Only xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd was missing this patch

AxiStreamConcat.vhd Update
Author: Larry Ruckman [email protected]
Date: Fri Sep 1 10:01:22 2023 -0700
Pull: #1110 (18 additions, 9 deletions, 1 files changed)
Branch: slaclab/AxiStreamConcat-patch

Notes:

Description

  • fixed REG_INIT_C syntax bug and general clean up
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Minor Release v2.44.0

22 Jul 01:32
@ruck314 ruck314
v2.44.0
c9f42ce
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Minor Release v2.44.0

Pull Requests Since v2.43.0

Bug

  1. #1097 - Fix ADC python code using list Variables

Enhancement

  1. #1093 - Remove legacy rawWrite/rawRead and remove MemoryDevice

Unlabeled

  1. #1091 - Adding line-code encode/decode modules to cocoTB CI regression testing
  2. #1098 - Adding more cocoTB modules
  3. #1092 - Adding AxiStreamFifoV2 to cocoTB CI regression testing
  4. #1099 - Provide register init values for PGP2b
  5. #1096 - cocoTB update and Bug fixes for AxiStreamGearbox.vhd
  6. #1090 - adding enAdcTile/enDacTile arg to _RfDataConverter.py
  7. #1094 - allowing RF block in gen1 type
  8. #1089 - fix Delay3PatchFSM: init issue (JIRA ESSURF-24)

Pull Request Details

fix Delay3PatchFSM: init issue (JIRA ESSURF-24)
Author: Larry Ruckman [email protected]
Date: Tue Jun 27 07:40:33 2023 -0700
Pull: #1089 (13 additions, 8 deletions, 1 files changed)
Branch: slaclab/delay3patch_fix

Notes:

Fixing init bug of the delay3PatchFSM

Description

I added an additional step named CHECK_CNT_S. IT handles the logic previously located in the IDLE_S state. Then, the IDLE_S has been changed to wait for a load command. The FSM goes to CHECK_CNT_S after loading where the logic check if the CNTINVALUE has to be inc/dec. Finally, if the FSM has reached the expect value, it goes back to IDLE_S and wait for a new LOAD_S.

Details

Side effect: no new value can be load until busy signal goes back to low.

JIRA

ESSURF-24

adding enAdcTile/enDacTile arg to _RfDataConverter.py
Author: Larry Ruckman [email protected]
Date: Mon Jul 3 10:26:28 2023 -0700
Pull: #1090 (19 additions, 15 deletions, 1 files changed)
Branch: slaclab/RfDataConverter-dev

Notes:

Description

  • Required for RFSoC application that do not have or do not build all 4 ADC or all 4 DAC tiles

Adding line-code encode/decode modules to cocoTB CI regression testing
Author: Larry Ruckman [email protected]
Date: Sat Jul 8 10:00:23 2023 -0700
Pull: #1091 (849 additions, 7 deletions, 11 files changed)
Branch: slaclab/ESSURF-21
Jira: https://jira.slac.stanford.edu/issues/ESSURF-21

Notes:

Description

Adding AxiStreamFifoV2 to cocoTB CI regression testing
Author: Larry Ruckman [email protected]
Date: Thu Jul 6 14:54:01 2023 -0700
Pull: #1092 (460 additions, 12 deletions, 6 files changed)
Branch: slaclab/AxiStreamFifoV2IpIntegrator

Notes:

Description

Remove legacy rawWrite/rawRead and remove MemoryDevice
Author: Larry Ruckman [email protected]
Date: Thu Jul 6 15:25:55 2023 -0700
Pull: #1093 (763 additions, 1313 deletions, 11 files changed)
Branch: slaclab/rogue_v6
Labels: enhancement

Notes:

Remove legacy rawWrite/rawRead and remove MemoryDevice

allowing RF block in gen1 type
Author: Larry Ruckman [email protected]
Date: Thu Jul 13 13:45:57 2023 -0700
Pull: #1094 (10 additions, 11 deletions, 1 files changed)
Branch: slaclab/rfsoc-gen1-dev

Notes:

Description

  • Confirmed that this RF block for setting NCO values in gen1 RFSoC works

cocoTB update and Bug fixes for AxiStreamGearbox.vhd
Author: Larry Ruckman [email protected]
Date: Thu Jul 13 14:35:14 2023 -0700
Pull: #1096 (36 additions, 15 deletions, 7 files changed)
Branch: slaclab/ESCORE-818
Jira: https://jira.slac.stanford.edu/issues/ESCORE-818

Notes:

Description

Fix ADC python code using list Variables
Author: Larry Ruckman [email protected]
Date: Thu Jul 13 14:02:42 2023 -0700
Pull: #1097 (209 additions, 279 deletions, 2 files changed)
Branch: slaclab/rogue_v6
Labels: bug

Notes:

The previous code had mistakes in the list variable mappings.

Best to compare to the original rawWrite code:

https://github.com/slaclab/surf/blob/master/python/surf/devices/ti/_Adc32Rf45.py

Adding more cocoTB modules
Author: Larry Ruckman [email protected]
Date: Fri Jul 21 17:29:48 2023 -0700
Pull: #1098 (812 additions, 4 deletions, 7 files changed)
Branch: slaclab/ESCORE-814
Jira: https://jira.slac.stanford.edu/issues/ESCORE-814

Notes:

Description

Provide register init values for PGP2b
Author: Benjamin Reese [email protected]
Date: Fri Jul 21 17:08:08 2023 -0700
Pull: #1099 (54 additions, 135 deletions, 4 files changed)
Branch: slaclab/pgp2b-init

Notes:

Description

PGP2b was coded using the older VHDL style, and so the registers did not have GSR init values. This was causing 'X' values to propagate into the GT during simulation. Once this happens, the 'X' values get stuck even after reseting the GT.

This change adds default values for all TX related registers so that 'X' values do not propagate into a simulated GT.

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Minor Release v2.43.0

17 Jun 06:23
@ruck314 ruck314
v2.43.0
b40b1e3
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Minor Release v2.43.0

Pull Requests Since v2.42.0

Enhancement

  1. #1083 - Add support for list variables in LMX2615

Unlabeled

  1. #1082 - Xvc wrapper merge
  2. #1085 - update for ClinkFraming.vhd
  3. #1087 - Allow some Adc32Rf45 parameters to be loaded via yaml
  4. #1081 - Update surf_ci.yml
  5. #1088 - bug fix for PgpXvcWrapper.vhd
  6. #1084 - Update to PgpTxVcFifo.vhd
  7. #1080 - updating microblaze/ruckus.tcl
  8. #1079 - _RfDataConverter.py Bug Fix

Pull Request Details

_RfDataConverter.py Bug Fix
Author: Larry Ruckman [email protected]
Date: Thu May 11 17:17:40 2023 -0700
Pull: #1079 (3 additions, 0 deletions, 1 files changed)
Branch: slaclab/RfDataConverter-update

Notes:

Description

  • bug fix to the RfDataConverter.Init() process

updating microblaze/ruckus.tcl
Author: Larry Ruckman [email protected]
Date: Fri May 19 09:50:54 2023 -0700
Pull: #1080 (2 additions, 1 deletions, 1 files changed)
Branch: slaclab/vivado-2023-1

Notes:

Description

  • Vivado 2023.1 did NOT fix the bug with AXI GPIO and system processor reset IP core blocks
  • This issue started in Vivado 2022.2 release

Update surf_ci.yml
Author: Larry Ruckman [email protected]
Date: Wed Jun 7 14:15:01 2023 -0700
Pull: #1081 (2 additions, 9 deletions, 1 files changed)
Branch: slaclab/ESROGUE-619
Jira: https://jira.slac.stanford.edu/issues/ESROGUE-619

Notes:

Description

  • No longer generating anaconda for pre-release

Xvc wrapper merge
Author: Larry Ruckman [email protected]
Date: Tue Jun 13 14:00:48 2023 -0700
Pull: #1082 (270 additions, 5 deletions, 6 files changed)
Branch: slaclab/xvc-wrapper

Notes:

XVC Wrapper is supposed to ease deployment of the XVC-over-PGP.

Add support for list variables in LMX2615
Author: Larry Ruckman [email protected]
Date: Tue Jun 13 09:21:30 2023 -0700
Pull: #1083 (38 additions, 4 deletions, 1 files changed)
Branch: slaclab/rogue_v6
Labels: enhancement

Notes:

This is the one device which did not avoid using rawWrite with Rogue versions past 5.4.

Update to PgpTxVcFifo.vhd
Author: Larry Ruckman [email protected]
Date: Tue Jun 13 08:57:27 2023 -0700
Pull: #1084 (3 additions, 0 deletions, 1 files changed)
Branch: slaclab/PgpTxVcFifo

Notes:

Description

  • adding support for CASCADE_SIZE_G

update for ClinkFraming.vhd
Author: Larry Ruckman [email protected]
Date: Tue Jun 13 12:40:39 2023 -0700
Pull: #1085 (33 additions, 2 deletions, 1 files changed)
Branch: slaclab/clink-deca-mode

Notes:

Description

  • No ZERO padding for DECA mode

Allow some Adc32Rf45 parameters to be loaded via yaml
Author: Benjamin Reese [email protected]
Date: Fri Jun 16 15:30:07 2023 -0700
Pull: #1087 (18 additions, 6 deletions, 2 files changed)
Branch: slaclab/512fft-tkid2

Notes:

Description

Previously, the DDC parameters were hard coded and written during the init routine.
Now they are given default values and allowed to be overridden by a yaml file.

bug fix for PgpXvcWrapper.vhd
Author: Larry Ruckman [email protected]
Date: Fri Jun 16 13:27:52 2023 -0700
Pull: #1088 (1 additions, 2 deletions, 1 files changed)
Branch: slaclab/xvc-wrapper-patch

Notes:

Description

  • Removed output port that doesn't exists
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Minor Release v2.42.0

24 Apr 19:39
@ruck314 ruck314
v2.42.0
c52c352
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Minor Release v2.42.0

Pull Requests Since v2.41.0

Unlabeled

  1. #1061 - Add Rogue Devices for Xilinx GTYE4 DRP Registers
  2. #1068 - adding more RST_ASYNC_G support
  3. #1072 - Adding VHDL Regression Testing to CI workflow
  4. #1074 - Delete AxiStreamFifo.vhd
  5. #1075 - Ruckus tcl fix
  6. #1071 - Delete releaseNotes.py
  7. #1073 - AxiLiteCrossbarI2cMux.vhd update

Pull Request Details

Add Rogue Devices for Xilinx GTYE4 DRP Registers
Author: Benjamin Reese [email protected]
Date: Tue Apr 18 11:22:55 2023 -0700
Pull: #1061 (4761 additions, 0 deletions, 3 files changed)
Branch: slaclab/gtye4-rogue

Notes:

Description

Add Rogue Devices for GTY DRP registers.

adding more RST_ASYNC_G support
Author: Larry Ruckman [email protected]
Date: Mon Apr 24 10:54:02 2023 -0700
Pull: #1068 (1172 additions, 834 deletions, 152 files changed)
Branch: slaclab/ESCORE-782
Jira: https://jira.slac.stanford.edu/issues/ESCORE-782

Notes:

Description

  • Required for ASIC digital designs that are fundamentally ASYNC resets for all FFs

Delete releaseNotes.py
Author: Larry Ruckman [email protected]
Date: Tue Apr 11 07:29:33 2023 -0700
Pull: #1071 (0 additions, 179 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

Adding VHDL Regression Testing to CI workflow
Author: Larry Ruckman [email protected]
Date: Fri Apr 21 09:34:46 2023 -0700
Pull: #1072 (614 additions, 635 deletions, 182 files changed)
Branch: slaclab/ESCORE-730
Issues: #1072
Jira: https://jira.slac.stanford.edu/issues/ESCORE-730

Notes:

Description

  • Based on cocoTB and GHDL v3.0.0
    • Using standard pytest with code coverage
    • New ruckus + GHDL support to load existing ruckus.tcl scripts
  • Updating ruckus submodule lock to v4.8.0
    • Required for $::env(RUCKUS_PROC_TCL_COMBO) support

GHDL Warning Resolving

During code review, the following should be looked at careful to make sure behavior didn't change:

  • axi/axi-lite/rtl/AxiLitePkg.vhd
  • axi/axi4/rtl/AxiPkg.vhd
  • base/general/rtl/TextUtilPkg.vhd
  • protocols/ssi/rtl/SsiPkg.vhd

AxiLiteCrossbarI2cMux.vhd update
Author: Larry Ruckman [email protected]
Date: Tue Apr 18 10:26:34 2023 -0700
Pull: #1073 (2 additions, 0 deletions, 1 files changed)
Branch: slaclab/AxiLiteCrossbarI2cMux-dev

Notes:

Description

  • adding active HIGH I2C RST output port, which is useful to have in some applications

Delete AxiStreamFifo.vhd
Author: Larry Ruckman [email protected]
Date: Fri Apr 21 13:48:14 2023 -0700
Pull: #1074 (0 additions, 657 deletions, 1 files changed)
Branch: slaclab/AxiStreamFifo-vhd-Depreciating

Notes:

Description

  • Depreciating and deleting AxiStreamFifo.vhd
  • Everyone should be transitioned to AxiStreamFifo.V2vhd at this point

Ruckus tcl fix
Author: Larry Ruckman [email protected]
Date: Mon Apr 24 10:43:33 2023 -0700
Pull: #1075 (170 additions, 170 deletions, 168 files changed)
Branch: slaclab/ruckus-tcl-fix

Notes:

Description

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Minor Release v2.41.0

08 Apr 14:15
@ruck314 ruck314
v2.41.0
db98a64
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Minor Release v2.41.0

Pull Requests Since v2.40.0

Enhancement

  1. #1064 - Fix anaconda build
  2. #1067 - Set min python version to 3.7
  3. #1059 - Remove Python Version Limitation

Unlabeled

  1. #1069 - Removing Legacy Modules
  2. #1062 - adding Init() function to RfDataConverter.py
  3. #1063 - updating .gitignore
  4. #1066 - Fix upload directory
  5. #1060 - AxiPciePhy.py bug fix
  6. #1065 - Fix for conda build

Pull Request Details

Remove Python Version Limitation
Author: Larry Ruckman [email protected]
Date: Tue Apr 4 11:06:25 2023 -0700
Pull: #1059 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/conda_fix
Labels: enhancement

Notes:

The previous version had python locked to 3.7 which was making it hard to find solutions. This opens up the python verion.

AxiPciePhy.py bug fix
Author: Larry Ruckman [email protected]
Date: Wed Apr 5 09:54:16 2023 -0700
Pull: #1060 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/AxiPciePhy-bug-fix-16lanes

Notes:

Description

  • Resolve the issue where 16 lanes was reporting zero lanes

adding Init() function to RfDataConverter.py
Author: Larry Ruckman [email protected]
Date: Sat Apr 8 06:59:21 2023 -0700
Pull: #1062 (26 additions, 3 deletions, 1 files changed)
Branch: slaclab/rfdc-init

Notes:

Description

  • Moving this init code that was copy/pasted in multiple root classes into the RFDC device class

updating .gitignore
Author: Larry Ruckman [email protected]
Date: Sat Apr 8 06:59:41 2023 -0700
Pull: #1063 (3 additions, 0 deletions, 1 files changed)
Branch: slaclab/gitignore-update

Notes:

Description

  • ignoring EMACS temp files

Fix anaconda build
Author: Larry Ruckman [email protected]
Date: Thu Apr 6 18:36:14 2023 -0700
Pull: #1064 (11 additions, 6 deletions, 4 files changed)
Branch: slaclab/conda_fix
Labels: enhancement

Notes:

Adds new solver library
Updates meta file structure
Uses pip for python install

This package is now built as a noarch

Fix for conda build
Author: Larry Ruckman [email protected]
Date: Thu Apr 6 19:06:03 2023 -0700
Pull: #1065 (0 additions, 1 deletions, 1 files changed)
Branch: slaclab/conda_fix2

Notes:

Remove Conda Update

Fix upload directory
Author: Larry Ruckman [email protected]
Date: Thu Apr 6 19:20:32 2023 -0700
Pull: #1066 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/conda_fix2

Notes:

Fix upload source directory.

Set min python version to 3.7
Author: Larry Ruckman [email protected]
Date: Fri Apr 7 10:21:18 2023 -0700
Pull: #1067 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/min_python
Labels: enhancement

Notes:

This set the min python version to 3.7.

Removing Legacy Modules
Author: Larry Ruckman [email protected]
Date: Sat Apr 8 06:59:57 2023 -0700
Pull: #1069 (0 additions, 735 deletions, 4 files changed)
Branch: slaclab/obsolete-removal

Notes:

Description

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Minor Release v2.40.0

03 Apr 18:14
@ruck314 ruck314
v2.40.0
f771285
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Minor Release v2.40.0

Pull Requests Since v2.39.0

Unlabeled

  1. #1056 - bug fix for AxiLitePkg.vhd to make AxiLiteWrite work for Cadence Genus
  2. #1057 - Sugoi Post-Synthesis Simulation Reset Support

Pull Request Details

bug fix for AxiLitePkg.vhd to make AxiLiteWrite work for Cadence Genus
Author: Larry Ruckman [email protected]
Date: Mon Apr 3 11:08:44 2023 -0700
Pull: #1056 (96 additions, 8 deletions, 1 files changed)
Branch: slaclab/axi-lite-genus-dev

Notes:

Description

  • With the default of constVal = "X", Cadence Genus quietly fails to synthesis the if (constVal /= "X") then statement and optimizes the write data bus away away in synthesis
  • This proposed solution is just add more function overloading for the constVal argument is not used

Sugoi Post-Synthesis Simulation Reset Support
Author: Larry Ruckman [email protected]
Date: Fri Mar 31 10:44:42 2023 -0700
Pull: #1057 (44 additions, 24 deletions, 5 files changed)
Branch: slaclab/sugoi-RST_ASYNC_G

Notes:

Description

  • adding RST_ASYNC_G support to these modules so we can do a ASYNC reset at power up after ASIC post-synthsis.
  • This removes the 'X' signals such that '+vcs+initreg+0' is nolonger required
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Minor Release v2.39.0

28 Mar 22:55
@ruck314 ruck314
v2.39.0
473e1a3
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Minor Release v2.39.0

Pull Requests Since v2.38.1

Unlabeled

  1. #1053 - Updates to xilinx/_RfDataConverter.py
  2. #1055 - Bug fixes _RfBlock.py

Pull Request Details

Updates to xilinx/_RfDataConverter.py
Author: Larry Ruckman [email protected]
Date: Mon Mar 27 15:52:21 2023 -0700
Pull: #1053 (296 additions, 0 deletions, 4 files changed)
Branch: slaclab/rfdc-dev

Notes:

Description

  • Add rfdc support for mixer registers
  • Adding python/surf/xilinx/_RfBlock.py

Bug fixes _RfBlock.py
Author: Larry Ruckman [email protected]
Date: Tue Mar 28 15:49:31 2023 -0700
Pull: #1055 (92 additions, 145 deletions, 3 files changed)
Branch: slaclab/rfdc-dev-bug-fix

Notes:

Description

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Patch Release v2.38.1

21 Mar 18:35
@ruck314 ruck314
v2.38.1
d9db0b5
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Patch Release v2.38.1

Pull Requests Since v2.38.0

Unlabeled

  1. #1051 - Bug fix for AxiStreamDmaRingWrite.vhd
  2. #1046 - Pass PAYLOAD_CNT_TOP_G to Pgp2bTxCell

Pull Request Details

Pass PAYLOAD_CNT_TOP_G to Pgp2bTxCell
Author: Larry Ruckman [email protected]
Date: Tue Mar 21 09:17:23 2023 -0700
Pull: #1046 (2 additions, 1 deletions, 1 files changed)
Branch: slaclab/pgp2b-fix

Notes:

Description

@cbakalis-slac noticed that in Pgp2bTx.vhd, PAYLOAD_CNT_TOP_G was not being passed down into Pgp2bTxCell.

Bug fix for AxiStreamDmaRingWrite.vhd
Author: Larry Ruckman [email protected]
Date: Tue Mar 21 10:37:49 2023 -0700
Pull: #1051 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/v2.37.2-first-burst-fix

Notes:

Description

  • Fix my bug that wrote the first burst to the wrong address after init.

Contributors

cbakalis-slac
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Patch Release v2.37.2

09 Mar 19:00
@ruck314 ruck314
v2.37.2
6a4c027
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Patch Release v2.37.2

Pull Requests Since v2.37.1

Unlabeled

  1. #1043 - Fix bufferClear mechanism in AxiStreamDmaRingWrite

Pull Request Details

Fix bufferClear mechanism in AxiStreamDmaRingWrite
Author: Larry Ruckman [email protected]
Date: Thu Mar 9 10:37:10 2023 -0800
Pull: #1043 (71 additions, 44 deletions, 1 files changed)
Branch: slaclab/v2.36.0-bufferclear

Notes:

Modify AxiStreamDmaRingWrite module so that the bufferClear input does not corrupt the status or write pointers of other buffers

Fix the bufferClear mechanism in AxiStreamDmaRingWrite.vhd so it no longer corrupts other dma buffers in progress.

Description

The AxiStreamDmaRingWrite module has an input signal bufferClearEn/Addr for clearing any buffer. This feature competes with the state machine that manages the dma address pointers and status for the incoming axisDataMaster. Previously, the bufferClearEn could corrupt both the status and address pointers for one buffer while clearing another. The status update from bufferClearEn is handled promptly, unless a current write to status is underway by the state machine. The address pointer reset from bufferClearEn is cached until the state machine gets to it.

Details

JIRA

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Patch Release v2.37.1

08 Mar 05:37
@ruck314 ruck314
v2.37.1
2763228
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Patch Release v2.37.1

Pull Requests Since v2.37.0

Unlabeled

  1. #1041 - Updating Si5345Lite.py
  2. #1039 - Updates for Cadence Genus Synthesis + Building PGP into an ASIC Support
  3. #1042 - AxiPciePhy.py bug fix
  4. #1036 - Update LICENSE.txt

Pull Request Details

Update LICENSE.txt
Author: Larry Ruckman [email protected]
Date: Thu Feb 16 19:37:50 2023 -0800
Pull: #1036 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Updating for 2023

Updates for Cadence Genus Synthesis + Building PGP into an ASIC Support
Author: Larry Ruckman [email protected]
Date: Tue Mar 7 09:45:53 2023 -0800
Pull: #1039 (123 additions, 87 deletions, 14 files changed)
Branch: slaclab/cadence-genus

Notes:

Description

Updating Si5345Lite.py
Author: Larry Ruckman [email protected]
Date: Tue Mar 7 21:00:24 2023 -0800
Pull: #1041 (306 additions, 2376 deletions, 2 files changed)
Branch: slaclab/SI5345-dev

Notes:

Description

  • removing overlap variables and using LinkVariables instead

AxiPciePhy.py bug fix
Author: Larry Ruckman [email protected]
Date: Tue Mar 7 21:27:46 2023 -0800
Pull: #1042 (31 additions, 52 deletions, 1 files changed)
Branch: slaclab/AxiPciePhy

Notes:

Description

  • Fixed the issue where PCIe GEN4, GEN5 and GEN6 were not displaying LnkStaSpeed and LnkCapSpeed properly
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