Minor Release v2.44.0
Pull Requests Since v2.43.0
Bug
- #1097 - Fix ADC python code using list Variables
Enhancement
- #1093 - Remove legacy rawWrite/rawRead and remove MemoryDevice
Unlabeled
- #1091 - Adding line-code encode/decode modules to cocoTB CI regression testing
- #1098 - Adding more cocoTB modules
- #1092 - Adding AxiStreamFifoV2 to cocoTB CI regression testing
- #1099 - Provide register init values for PGP2b
- #1096 - cocoTB update and Bug fixes for AxiStreamGearbox.vhd
- #1090 - adding enAdcTile/enDacTile arg to _RfDataConverter.py
- #1094 - allowing RF block in gen1 type
- #1089 - fix Delay3PatchFSM: init issue (JIRA ESSURF-24)
Pull Request Details
fix Delay3PatchFSM: init issue (JIRA ESSURF-24)
| Author: | Larry Ruckman [email protected] |
| Date: | Tue Jun 27 07:40:33 2023 -0700 |
| Pull: | #1089 (13 additions, 8 deletions, 1 files changed) |
| Branch: | slaclab/delay3patch_fix |
Notes:
Fixing init bug of the delay3PatchFSM
Description
I added an additional step named CHECK_CNT_S. IT handles the logic previously located in the IDLE_S state. Then, the IDLE_S has been changed to wait for a load command. The FSM goes to CHECK_CNT_S after loading where the logic check if the CNTINVALUE has to be inc/dec. Finally, if the FSM has reached the expect value, it goes back to IDLE_S and wait for a new LOAD_S.
Details
Side effect: no new value can be load until busy signal goes back to low.
JIRA
adding enAdcTile/enDacTile arg to _RfDataConverter.py
| Author: | Larry Ruckman [email protected] |
| Date: | Mon Jul 3 10:26:28 2023 -0700 |
| Pull: | #1090 (19 additions, 15 deletions, 1 files changed) |
| Branch: | slaclab/RfDataConverter-dev |
Notes:
Description
- Required for RFSoC application that do not have or do not build all 4 ADC or all 4 DAC tiles
Adding line-code encode/decode modules to cocoTB CI regression testing
| Author: | Larry Ruckman [email protected] |
| Date: | Sat Jul 8 10:00:23 2023 -0700 |
| Pull: | #1091 (849 additions, 7 deletions, 11 files changed) |
| Branch: | slaclab/ESSURF-21 |
| Jira: | https://jira.slac.stanford.edu/issues/ESSURF-21 |
Notes:
Description
Adding AxiStreamFifoV2 to cocoTB CI regression testing
| Author: | Larry Ruckman [email protected] |
| Date: | Thu Jul 6 14:54:01 2023 -0700 |
| Pull: | #1092 (460 additions, 12 deletions, 6 files changed) |
| Branch: | slaclab/AxiStreamFifoV2IpIntegrator |
Notes:
Description
- SUGOI sim includes library UNISIM
- adding AxiStreamFifoV2IpIntegrator.vhd
- Added test_AxiStreamFifoV2IpIntegrator.py
- updating ruckus submodule lock due to cocoTB/GHDL deps
Remove legacy rawWrite/rawRead and remove MemoryDevice
| Author: | Larry Ruckman [email protected] |
| Date: | Thu Jul 6 15:25:55 2023 -0700 |
| Pull: | #1093 (763 additions, 1313 deletions, 11 files changed) |
| Branch: | slaclab/rogue_v6 |
| Labels: | enhancement |
Notes:
Remove legacy rawWrite/rawRead and remove MemoryDevice
allowing RF block in gen1 type
| Author: | Larry Ruckman [email protected] |
| Date: | Thu Jul 13 13:45:57 2023 -0700 |
| Pull: | #1094 (10 additions, 11 deletions, 1 files changed) |
| Branch: | slaclab/rfsoc-gen1-dev |
Notes:
Description
- Confirmed that this RF block for setting NCO values in gen1 RFSoC works
cocoTB update and Bug fixes for AxiStreamGearbox.vhd
| Author: | Larry Ruckman [email protected] |
| Date: | Thu Jul 13 14:35:14 2023 -0700 |
| Pull: | #1096 (36 additions, 15 deletions, 7 files changed) |
| Branch: | slaclab/ESCORE-818 |
| Jira: | https://jira.slac.stanford.edu/issues/ESCORE-818 |
Notes:
Description
- migrating from .VCD to .GHW because GHW supports record type dumps
- Bug fixes for AxiStreamGearbox.vhd when (SLV_BYTES_C>MST_BYTES_C) and (transfer size < MST_BYTES_C)
- Prevents the tkeep=0 w/ tLast case
- bug fixes for AxiStreamGearbox.vhd for when (SLV_BYTES_C>2*MST_BYTES_C) and terminating a frame
- Prevent the case there the tLast was getting asserted too early
- updating paramSweep to include non-word multiple to execise AxiStreamGearbox
Fix ADC python code using list Variables
| Author: | Larry Ruckman [email protected] |
| Date: | Thu Jul 13 14:02:42 2023 -0700 |
| Pull: | #1097 (209 additions, 279 deletions, 2 files changed) |
| Branch: | slaclab/rogue_v6 |
| Labels: | bug |
Notes:
The previous code had mistakes in the list variable mappings.
Best to compare to the original rawWrite code:
https://github.com/slaclab/surf/blob/master/python/surf/devices/ti/_Adc32Rf45.py
Adding more cocoTB modules
| Author: | Larry Ruckman [email protected] |
| Date: | Fri Jul 21 17:29:48 2023 -0700 |
| Pull: | #1098 (812 additions, 4 deletions, 7 files changed) |
| Branch: | slaclab/ESCORE-814 |
| Jira: | https://jira.slac.stanford.edu/issues/ESCORE-814 |
Notes:
Description
Provide register init values for PGP2b
| Author: | Benjamin Reese [email protected] |
| Date: | Fri Jul 21 17:08:08 2023 -0700 |
| Pull: | #1099 (54 additions, 135 deletions, 4 files changed) |
| Branch: | slaclab/pgp2b-init |
Notes:
Description
PGP2b was coded using the older VHDL style, and so the registers did not have GSR init values. This was causing 'X' values to propagate into the GT during simulation. Once this happens, the 'X' values get stuck even after reseting the GT.
This change adds default values for all TX related registers so that 'X' values do not propagate into a simulated GT.