Merge pull request #1050 from slaclab/pre-release

Release Candidate v2.38.1
slaclab · Mar 21, 2023 · d9db0b5 · d9db0b5
2 parents b0a1a67 + e00970b
commit d9db0b5
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Showing 2 changed files with 4 additions and 3 deletions.
diff --git a/axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd b/axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd
@@ -569,8 +569,8 @@ begin
             -- Direct that frame be dropped if buffer is done with trigger sequence
             -- Writes always start on a BURST_SIZE_BYTES_G boundary, so can drive low dmaReq.address
             -- bits to zero for optimization.
-            v.dmaReq.address(AXI_WRITE_CONFIG_G.ADDR_WIDTH_C-1 downto 0) := nextRamDout;
-            endRamSize := conv_integer(endRamDout - nextRamDout);
+            v.dmaReq.address(AXI_WRITE_CONFIG_G.ADDR_WIDTH_C-1 downto 0) := v.nextAddr;
+            endRamSize := conv_integer(endRamDout - v.nextAddr);
             if FORCE_WRAP_ALIGN_G and endRamSize < BURST_SIZE_BYTES_G then
               v.dmaReq.maxSize := toSlv(endRamSize, 32);
             else

diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTx.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTx.vhd
@@ -239,7 +239,8 @@ begin
    U_Pgp2bTxCell: entity surf.Pgp2bTxCell
       generic map (
          TPD_G             => TPD_G,
-         TX_LANE_CNT_G     => TX_LANE_CNT_G
+         TX_LANE_CNT_G     => TX_LANE_CNT_G,
+         PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G
       ) port map (
          pgpTxClkEn        => pgpTxClkEn,
          pgpTxClk          => pgpTxClk,