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@ruck314 ruck314 released this 09 Mar 19:00
· 707 commits to main since this release
v2.37.2
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Pull Requests Since v2.37.1

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  1. #1043 - Fix bufferClear mechanism in AxiStreamDmaRingWrite

Pull Request Details

Fix bufferClear mechanism in AxiStreamDmaRingWrite
Author: Larry Ruckman [email protected]
Date: Thu Mar 9 10:37:10 2023 -0800
Pull: #1043 (71 additions, 44 deletions, 1 files changed)
Branch: slaclab/v2.36.0-bufferclear

Notes:

Modify AxiStreamDmaRingWrite module so that the bufferClear input does not corrupt the status or write pointers of other buffers

Fix the bufferClear mechanism in AxiStreamDmaRingWrite.vhd so it no longer corrupts other dma buffers in progress.

Description

The AxiStreamDmaRingWrite module has an input signal bufferClearEn/Addr for clearing any buffer. This feature competes with the state machine that manages the dma address pointers and status for the incoming axisDataMaster. Previously, the bufferClearEn could corrupt both the status and address pointers for one buffer while clearing another. The status update from bufferClearEn is handled promptly, unless a current write to status is underway by the state machine. The address pointer reset from bufferClearEn is cached until the state machine gets to it.

Details

JIRA

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