Merge pull request #1076 from slaclab/pre-release

Release Candidate v2.42.0
slaclab · Apr 24, 2023 · c52c352 · c52c352
2 parents db98a64 + 5a83c08
commit c52c352
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diff --git a/.github/workflows/surf_ci.yml b/.github/workflows/surf_ci.yml
@@ -19,38 +19,52 @@ on: [push]
 
 jobs:
 
+# ----------------------------------------------------------------------------
+
   test_and_document:
     name: Test And Generate Documentation
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
     steps:
 
       # This step checks out a copy of your repository.
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v3
         with:
           fetch-depth: 0
 
-      - uses: actions/setup-python@v2
+      - uses: actions/setup-python@v4
         with:
-          python-version: 3.8
+          python-version: 3.11
 
       - name: Install dependencies
         run: |
           sudo apt-get update
-          sudo apt-get install doxygen doxygen-doc doxygen-latex doxygen-gui graphviz ghdl
+          sudo apt-get install make python3 python3-pip tclsh
+          sudo apt-get install doxygen doxygen-doc doxygen-latex doxygen-gui graphviz
           python -m pip install --upgrade pip
-          pip install flake8
+          pip install -r pip_requirements.txt
+          git clone https://github.com/slaclab/ruckus.git
+          pip install -r ruckus/scripts/pip_requirements.txt
 
-      - name: VHDL Syntax Check
+      - name: Python Syntax and Linter Checking
         run: |
-          make
-          rm -rf ghdl-build
+          python -m compileall -f python/ scripts/ tests/
+          flake8 --count python/ scripts/ tests/
 
-      - name: Python Syntax Check
+      - name: VHDL Regression Testing
         run: |
-          python -m compileall -f python/
-          flake8 --count python/
+          ./ghdl-build.sh > /dev/null 2>&1
+          make MODULES=$PWD
+          python -m pytest --cov -v tests/
+          rm -rf ghdl-build
+
+#      # Code Coverage
+#      - name: Code Coverage
+#        run: |
+#          codecov
+#          coverage report -m
 
       - name: Generate Documentation
+        if: startsWith(github.ref, 'refs/tags/') || github.ref == 'refs/heads/pre-release'
         run: |
           doxygen Doxyfile
 
@@ -61,6 +75,8 @@ jobs:
           github_token: ${{ secrets.GH_TOKEN }}
           publish_dir: doxygen/html
 
+# ----------------------------------------------------------------------------
+
   gen_release:
     name: Generate Release
     runs-on: ubuntu-20.04
@@ -95,6 +111,8 @@ jobs:
         run: |
           python ruckus/scripts/releaseGen.py
 
+# ----------------------------------------------------------------------------
+
   conda_build:
     name: Anaconda Build
     needs: [test_and_document]
@@ -154,3 +172,4 @@ jobs:
           conda build --debug conda-recipe --output-folder bld-dir -c tidair-tag -c tidair-packages -c conda-forge
           anaconda -t ${{ steps.get_image_info.outputs.token }} upload --force bld-dir/noarch/*.tar.bz2
 
+# ----------------------------------------------------------------------------
diff --git a/.gitignore b/.gitignore
@@ -10,6 +10,11 @@
 *.db
 *.log
 *.vho
+*.xml
 xvcSrv
 doxygen/
-ghdl/
+ghdl-build/
+ruckus/
+build/
+sim_build/
+.coverage
diff --git a/Makefile b/Makefile
@@ -1,105 +1,66 @@
-# Makefile automatically generated by ghdl
-# Version: GHDL 0.34-dev (2017-03-01) [Dunoon edition] - mcode code generator
-# Command used to generate this makefile:
-# ghdl --gen-makefile -v -P/afs/slac/g/reseng/vol20/ghdl/lib/ghdl/vendors/xilinx-vivado/ --workdir=work --ieee=synopsys -fexplicit -frelaxed-rules AxiLiteCrossbar
-
-GHDL=ghdl
-GHDL_WORKDIR=ghdl
-GHDLFLAGS= --workdir=${GHDL_WORKDIR} --work=surf --ieee=synopsys -fexplicit -frelaxed-rules  --warn-no-library
-GHDLRUNFLAGS=
-
-PATHS = $(shell find -type f -name '*.vhd')
-
-# Exclude all the VHDL2008 files: /usr/bin/ghdl-mcode:warning: library synopsys does not exists for v08
-# Exclude all exempt modules with same entity name
-EXCLUDE  = $(shell find ./ghdl-build/ -type f -name '*.vhd') \
-$(shell find ./dsp/logic/ -type f -name '*.vhd') \
-$(shell find . -type f -name '*Ad9249Deserializer.vhd') \
-$(shell find . -type f -name '*Ad9249ReadoutGroup.vhd') \
-$(shell find . -type f -name '*GigEthGthUltraScale.vhd') \
-$(shell find . -type f -name '*GigEthGthUltraScaleWrapper.vhd') \
-$(shell find . -type f -name '*TenGigEthGthUltraScale.vhd') \
-$(shell find . -type f -name '*TenGigEthGthUltraScaleClk.vhd') \
-$(shell find . -type f -name '*TenGigEthGthUltraScaleRst.vhd') \
-$(shell find . -type f -name '*TenGigEthGthUltraScaleWrapper.vhd') \
-$(shell find . -type f -name '*XauiGthUltraScale.vhd') \
-$(shell find . -type f -name '*XauiGthUltraScaleWrapper.vhd') \
-$(shell find . -type f -name '*ClinkDataClk.vhd') \
-$(shell find . -type f -name '*ClinkDataShift.vhd') \
-$(shell find . -type f -name '*Pgp2bGthUltra.vhd') \
-$(shell find . -type f -name '*PgpGthCoreWrapper.vhd') \
-$(shell find . -type f -name '*Pgp3GthUs.vhd') \
-$(shell find . -type f -name '*Pgp3GthUsIpWrapper.vhd') \
-$(shell find . -type f -name '*Pgp3GthUsQpll.vhd') \
-$(shell find . -type f -name '*Pgp3GthUsWrapper.vhd') \
-$(shell find . -type f -name '*InputBufferReg.vhd') \
-$(shell find . -type f -name '*OutputBufferReg.vhd') \
-$(shell find . -type f -name '*GthUltraScaleQuadPll.vhd') \
-$(shell find . -type f -name '*MicroblazeBasicCoreWrapper.vhd') \
-$(shell find . -type f -name '*ComplexFixedPkg.vhd') \
-$(shell find . -type f -name '*SfixedDelay.vhd') \
-$(shell find . -type f -name '*CfixedDelay.vhd') \
-$(shell find . -type f -name '*Csa3.vhd') \
-$(shell find . -type f -name '*Add3.vhd') \
-$(shell find . -type f -name '*SfixedPreAddMultAdd.vhd') \
-$(shell find . -type f -name '*SfixedMultAdd.vhd') \
-$(shell find . -type f -name '*SfixedMult.vhd') \
-$(shell find . -type f -name '*CfixedPreAddMult.vhd') \
-$(shell find . -type f -name '*CfixedMultAdd.vhd') \
-$(shell find . -type f -name '*CfixedMult.vhd') \
-$(shell find . -type f -name '*IirSimple.vhd') \
-$(shell find . -type f -name '*FirAverage.vhd') \
-$(shell find . -type f -name '*SinCosLut.vhd') \
-$(shell find . -type f -name '*SinCosTaylor.vhd')
-
-
-
-FILES = $(filter-out $(EXCLUDE),$(wildcard $(PATHS)))
-
-ENTITY_EXCLUDES = stdlib 
-
-ENTITIES := $(filter-out $(ENTITY_EXCLUDES),$(patsubst %Pkg,,$(patsubst %.vhd,%,$(notdir $(FILES)))))
-MAKEFILES = $(patsubst %,%.mk,$(ENTITIES))
-
-all: dir import
-
+#-----------------------------------------------------------------------------
+# This file is part of the 'SLAC Firmware Standard Library'. It is subject to
+# the license terms in the LICENSE.txt file found in the top-level directory
+# of this distribution and at:
+#    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+# No part of the 'SLAC Firmware Standard Library', including this file, may be
+# copied, modified, propagated, or distributed except according to the terms
+# contained in the LICENSE.txt file.
+#-----------------------------------------------------------------------------
+
+ifndef MODULES
+export MODULES = $(abspath $(PWD)/../)
+endif
+
+# GHDL/ruckus source loading
+export RUCKUS_DIR = $(MODULES)/ruckus
+export TOP_DIR    = $(abspath $(PWD))
+export PROJ_DIR   = $(abspath $(PWD))
+export OUT_DIR    = $(PROJ_DIR)/build
+
+# Path to GHDL proc.tcl
+export RUCKUS_PROC_TCL = $(RUCKUS_DIR)/ghdl/proc.tcl
+
+# Bypassing Xilinx Specific code
+export VIVADO_VERSION = -1.0
+
+# Override the submodule check because ruckus external of this repo
+export OVERRIDE_SUBMODULE_LOCKS = 1
+
+# GHDL build flags
+GHDLFLAGS = --workdir=$(OUT_DIR) --ieee=synopsys -fexplicit -frelaxed-rules  --warn-no-library
+
+# Include the shared ruckus Makefile header
+include $(RUCKUS_DIR)/system_shared.mk
+
+# Override system_shared.mk build string
+export BUILD_SVR_TYPE = $(shell python -m platform)
+export GHDL_VERSION   = $(shell ghdl -v 2>&1 | head -n 1)
+export BUILD_STRING   = $(PROJECT): $(GHDL_VERSION), $(BUILD_SYS_NAME) ($(BUILD_SVR_TYPE)), Built $(BUILD_DATE) by $(BUILD_USER)
+
+all: syntax
+
+# Test of the variables
+.PHONY : test
 test:
-	@echo GHDLFLAGS: $(GHDLFLAGS)
-	@echo FILES: $(FILES)
-	@echo ENTITIES:
-	@echo "\t$(foreach ARG,$(ENTITIES),  $(ARG)\n)"
-
-clean :
-	$(GHDL) --clean $(GHDLFLAGS)
-
-dir:
-	test -d $(GHDL_WORKDIR) || mkdir $(GHDL_WORKDIR)
-
-import : $(FILES)
-	@echo "============================================================================="
-	@echo Importing:
-	@echo "============================================================================="
-	$(GHDL) -i $(GHDLFLAGS) $(FILES)
-	$(GHDL) -i $(GHDLFLAGS) --std=08 $(EXCLUDE)
-
-syntax: $(FILES)
+	@echo PWD: $(PWD)
+	@echo MODULES: $(MODULES)
+	@echo RUCKUS_DIR: $(RUCKUS_DIR)
+	@echo PROJ_DIR: $(PROJ_DIR)
+	@echo OUT_DIR: $(OUT_DIR)
+	@echo RUCKUS_PROC_TCL: $(RUCKUS_PROC_TCL)
+	@echo VIVADO_VERSION: $(VIVADO_VERSION)
+
+# Find all the source code and load it into GHDL
+.PHONY : src
+src:
+	@$(RUCKUS_DIR)/ghdl/import.tcl > /dev/null 2>&1
+
+# Find all the source code and load it into GHDL
+.PHONY : syntax
+syntax: src
 	@echo "============================================================================="
-	@echo Syntax Checking:
+	@echo VHDL Syntax Checking:
 	@echo "============================================================================="
-	$(GHDL) -s $(GHDLFLAGS) $(FILES)
-	$(GHDL) -s $(GHDLFLAGS) --std=08 $(EXCLUDE)
-
-makefiles: $(MAKEFILES)
-
-elaborate: $(ENTITIES)
-
-$(ENTITIES) : import syntax
-	$(GHDL) -e $(GHDLFLAGS) $@
-
-html : $(FILES)
-	$(GHDL) --xref-html $(GHDLFLAGS) $(FILES)
-
-$(MAKEFILES) : import
-	$(GHDL) --gen-makefile $(GHDLFLAGS) $(patsubst %.mk,%,$@) > work/$@
-
-force:
+	@ghdl -i $(GHDLFLAGS) --work=surf   $(PROJ_DIR)/build/SRC_VHDL/surf/*
+	@ghdl -i $(GHDLFLAGS) --work=ruckus $(PROJ_DIR)/build/SRC_VHDL/ruckus/*
diff --git a/axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd
@@ -124,7 +124,6 @@ begin
          axilWriteSlave  => axilWriteSlave);
 
    process(userValues)
-      variable i      : natural;
       variable retVar : Slv32Array(0 to 63);
    begin
       for i in 0 to 63 loop

diff --git a/axi/axi-lite/rtl/AxiDualPortRam.vhd b/axi/axi-lite/rtl/AxiDualPortRam.vhd
@@ -25,6 +25,7 @@ use surf.AxiLitePkg.all;
 entity AxiDualPortRam is
    generic (
       TPD_G               : time                       := 1 ns;
+      RST_ASYNC_G         : boolean                    := false;
       SYNTH_MODE_G        : string                     := "inferred";
       MEMORY_TYPE_G       : string                     := "block";
       MEMORY_INIT_FILE_G  : string                     := "none";  -- Used for MEMORY_TYPE_G="XPM only
@@ -201,6 +202,7 @@ begin
          DualPortRam_1 : entity surf.DualPortRam
             generic map (
                TPD_G         => TPD_G,
+               RST_ASYNC_G   => RST_ASYNC_G,
                MEMORY_TYPE_G => MEMORY_TYPE_G,
                REG_EN_G      => ite(READ_LATENCY_G >= 1, true, false),
                DOA_REG_G     => ite(READ_LATENCY_G >= 2, true, false),
@@ -232,6 +234,7 @@ begin
          DualPortRam_1 : entity surf.DualPortRam
             generic map (
                TPD_G         => TPD_G,
+               RST_ASYNC_G   => RST_ASYNC_G,
                MEMORY_TYPE_G => MEMORY_TYPE_G,
                REG_EN_G      => ite(READ_LATENCY_G >= 1, true, false),
                DOA_REG_G     => ite(READ_LATENCY_G >= 2, true, false),
@@ -261,6 +264,7 @@ begin
          U_TrueDualPortRam_1 : entity surf.TrueDualPortRam
             generic map (
                TPD_G        => TPD_G,
+               RST_ASYNC_G  => RST_ASYNC_G,
                BYTE_WR_EN_G => true,
                DOA_REG_G    => ite(READ_LATENCY_G >= 2, true, false),
                DOB_REG_G    => ite(READ_LATENCY_G >= 2, true, false),
@@ -301,6 +305,7 @@ begin
    U_SynchronizerFifo_1 : entity surf.SynchronizerFifo
       generic map (
          TPD_G         => TPD_G,
+         RST_ASYNC_G   => RST_ASYNC_G,
          COMMON_CLK_G  => COMMON_CLK_G,
          MEMORY_TYPE_G => "distributed",
          DATA_WIDTH_G  => ADDR_WIDTH_G+DATA_WIDTH_G+ADDR_AXI_BYTES_C)
@@ -387,7 +392,7 @@ begin
       end case;
 
       -- Reset
-      if (axiRst = '1') then
+      if (RST_ASYNC_G = false and axiRst = '1') then
          v := REG_INIT_C;
       end if;
 
@@ -400,18 +405,22 @@ begin
 
    end process comb;
 
-   seq : process (axiClk) is
+   seq : process (axiClk, axiRst) is
    begin
-      if (rising_edge(axiClk)) then
+      if (RST_ASYNC_G and axiRst = '1') then
+         r <= REG_INIT_C after TPD_G;
+      elsif rising_edge(axiClk) then
          r <= rin after TPD_G;
       end if;
    end process seq;
 
    OUT_REG : if((READ_LATENCY_G = 3) and (SYNTH_MODE_G /= "xpm")) generate
-      REG : process (clk) is
+      REG : process (clk, rst) is
       begin
-         if(rising_edge(clk)) then
-            if (rst = '1') then
+         if (RST_ASYNC_G and rst = '1') then
+            dout <= (others => '0');
+         elsif (rising_edge(clk)) then
+            if (RST_ASYNC_G = false and rst = '1') then
                dout <= (others => '0');
             else
                dout <= doutInt;