Skip to content

Commit

Permalink
Merge pull request #1058 from slaclab/pre-release
Browse files Browse the repository at this point in the history 
Release Candidate v2.40.0
  • Loading branch information
@ruck314
ruck314 authored Apr 3, 2023
2 parents 473e1a3 + 6fa9191 commit f771285
Show file tree
Hide file tree
Showing 6 changed files with 140 additions and 32 deletions.
9 changes: 6 additions & 3 deletions axi/axi-lite/rtl/AxiLiteCrossbar.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@ entity AxiLiteCrossbar is

generic (
TPD_G : time := 1 ns;
RST_ASYNC_G : boolean := false;
NUM_SLAVE_SLOTS_G : natural range 1 to 16 := 4;
NUM_MASTER_SLOTS_G : natural range 1 to 64 := 4;
DEC_ERROR_RESP_G : slv(1 downto 0) := AXI_RESP_DECERR_C;
Expand Down Expand Up @@ -437,7 +438,7 @@ begin

end loop;

if (axiClkRst = '1') then
if (RST_ASYNC_G = false and axiClkRst = '1') then
v := REG_INIT_C;
end if;

Expand All @@ -450,9 +451,11 @@ begin

end process comb;

seq : process (axiClk) is
seq : process (axiClk, axiClkRst) is
begin
if (rising_edge(axiClk)) then
if (RST_ASYNC_G and axiClkRst = '1') then
r <= REG_INIT_C after TPD_G;
elsif rising_edge(axiClk) then
r <= rin after TPD_G;
end if;
end process seq;
Expand Down
104 changes: 96 additions & 8 deletions axi/axi-lite/rtl/AxiLitePkg.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -358,19 +358,18 @@ package AxiLitePkg is
variable axiWriteSlave : in AxiLiteWriteSlaveType;
variable axiReadSlave : in AxiLiteReadSlaveType);

procedure axiSlaveRegisterLegacy (
procedure axiSlaveRegister (
variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : inout slv;
constVal : in slv := "X");
constVal : in slv);

procedure axiSlaveRegister (
variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : inout slv;
constVal : in slv := "X");
reg : inout slv);

procedure axiSlaveRegisterR (
variable ep : inout AxiLiteEndpointType;
Expand All @@ -383,7 +382,13 @@ package AxiLitePkg is
addr : in slv;
offset : in integer;
reg : inout sl;
constVal : in sl := 'X');
constVal : in sl);

procedure axiSlaveRegister (
variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : inout sl);

procedure axiSlaveRegisterR (
variable ep : inout AxiLiteEndpointType;
Expand Down Expand Up @@ -747,7 +752,7 @@ package body AxiLitePkg is
addr : in slv;
offset : in integer;
reg : inout slv;
constVal : in slv := "X")
constVal : in slv)
is
-- Need to remap addr range to be (length-1 downto 0)
constant ADDR_LEN_C : integer := addr'length;
Expand Down Expand Up @@ -793,12 +798,62 @@ package body AxiLitePkg is

end procedure;

procedure axiSlaveRegisterLegacy (
variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : inout slv)
is
-- Need to remap addr range to be (length-1 downto 0)
constant ADDR_LEN_C : integer := addr'length;
constant ADDR_C : slv(ADDR_LEN_C-1 downto 0) := addr;
-- Offset as measured from addr[1:0]="00"
constant ABS_OFFSET_C : integer := offset + (to_integer(unsigned(ADDR_C(1 downto 0)))*8);
-- Normalized address and offset (for when addr[1:0]!=00)
constant NORMAL_ADDR_C : slv(ADDR_LEN_C-1 downto 0) := ite(ABS_OFFSET_C /= 0,
slv((unsigned(slv(ADDR_C))) + ((ABS_OFFSET_C/32)*4)),
ADDR_C);
constant NORMAL_OFFSET_C : integer := ABS_OFFSET_C mod 32;
-- Most significant register bit before wrapping to the next word address
constant REG_HIGH_BIT_C : integer := minimum(31-NORMAL_OFFSET_C+reg'low, reg'high);
-- Most significant data bus bit to be used in this recursion (max out at 31)
constant BUS_HIGH_BIT_C : integer := minimum(NORMAL_OFFSET_C+reg'length-1, 31);

variable strobeMask : slv(3 downto 0) := (others => '-');
begin

for i in BUS_HIGH_BIT_C downto NORMAL_OFFSET_C loop
strobeMask(i/8) := '1';
end loop;

-- Read must come first so as not to overwrite the variable if read and write happen at once
if (ep.axiStatus.readEnable = '1') then
if (std_match(ep.axiReadMaster.araddr(ADDR_LEN_C-1 downto 2), NORMAL_ADDR_C(ADDR_LEN_C-1 downto 2))) then
ep.axiReadSlave.rdata(BUS_HIGH_BIT_C downto NORMAL_OFFSET_C) := reg(REG_HIGH_BIT_C downto reg'low);
axiSlaveReadResponse(ep.axiReadSlave);
end if;
end if;

if (ep.axiStatus.writeEnable = '1') then
if (std_match(ep.axiWriteMaster.awaddr(ADDR_LEN_C-1 downto 2), NORMAL_ADDR_C(ADDR_LEN_C-1 downto 2)) and
std_match(ep.axiWriteMaster.wstrb, strobeMask)) then
-- if (constVal /= "X") then
-- reg(REG_HIGH_BIT_C downto reg'low) := resize(constVal,(REG_HIGH_BIT_C-reg'low)+1);
-- else
reg(REG_HIGH_BIT_C downto reg'low) := ep.axiWriteMaster.wdata(BUS_HIGH_BIT_C downto NORMAL_OFFSET_C);
-- end if;
axiSlaveWriteResponse(ep.axiWriteSlave);
end if;
end if;

end procedure;

procedure axiSlaveRegister (
variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : inout slv;
constVal : in slv := "X")
constVal : in slv)
is
variable highbit : integer;
begin
Expand All @@ -814,6 +869,26 @@ package body AxiLitePkg is

end procedure;

procedure axiSlaveRegister (
variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : inout slv)
is
variable highbit : integer;
begin

for i in ((reg'length-1)/32) downto 0 loop
if i = ((reg'length-1)/32) then
highbit := ((reg'length-1) mod 32) + (32*i) + reg'low;
else
highbit := 31 + (32*i) + reg'low;
end if;
axiSlaveRegisterLegacy(ep, slv(unsigned(addr)+(4*i)), offset, reg(highbit downto (32*i)+reg'low));
end loop;

end procedure;

procedure axiSlaveRegisterR (
variable ep : inout AxiLiteEndpointType;
addr : in slv;
Expand All @@ -833,7 +908,7 @@ package body AxiLitePkg is
addr : in slv;
offset : in integer;
reg : inout sl;
constVal : in sl := 'X')
constVal : in sl)
is
variable tmpReg : slv(0 downto 0);
variable tmpVal : slv(0 downto 0);
Expand All @@ -844,6 +919,19 @@ package body AxiLitePkg is
reg := tmpReg(0);
end procedure;

procedure axiSlaveRegister (
variable ep : inout AxiLiteEndpointType;
addr : in slv;
offset : in integer;
reg : inout sl)
is
variable tmpReg : slv(0 downto 0);
begin
tmpReg(0) := reg;
axiSlaveRegister(ep, addr, offset, tmpReg);
reg := tmpReg(0);
end procedure;

procedure axiSlaveRegisterR (
variable ep : inout AxiLiteEndpointType;
addr : in slv;
Expand Down
10 changes: 6 additions & 4 deletions axi/axi-lite/rtl/AxiVersion.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,14 +18,14 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


library surf;
use surf.StdRtlPkg.all;
use surf.AxiLitePkg.all;

entity AxiVersion is
generic (
TPD_G : time := 1 ns;
RST_ASYNC_G : boolean := false;
BUILD_INFO_G : BuildInfoType;
SIM_DNA_VALUE_G : slv := X"000000000000000000000000";
DEVICE_ID_G : slv(31 downto 0) := (others => '0');
Expand Down Expand Up @@ -223,7 +223,7 @@ begin
--------
-- Reset
--------
if (axiRst = '1') then
if (RST_ASYNC_G = false and axiRst = '1') then
v := REG_INIT_C;
end if;

Expand All @@ -240,9 +240,11 @@ begin

end process comb;

seq : process (axiClk) is
seq : process (axiClk, axiRst) is
begin
if (rising_edge(axiClk)) then
if (RST_ASYNC_G and axiRst = '1') then
r <= REG_INIT_C after TPD_G;
elsif rising_edge(axiClk) then
r <= rin after TPD_G;
end if;
end process seq;
Expand Down
11 changes: 7 additions & 4 deletions base/general/rtl/Gearbox.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@ use surf.StdRtlPkg.all;
entity Gearbox is
generic (
TPD_G : time := 1 ns;
RST_ASYNC_G : boolean := false;
SLAVE_BIT_REVERSE_G : boolean := false;
SLAVE_WIDTH_G : positive;
MASTER_BIT_REVERSE_G : boolean := false;
Expand Down Expand Up @@ -147,7 +148,7 @@ begin

slaveReady <= v.slaveReady;

if (rst = '1') then
if (RST_ASYNC_G = false and rst = '1') then
v := REG_INIT_C;
end if;

Expand All @@ -162,11 +163,13 @@ begin

end process comb;

sync : process (clk) is
seq : process (clk, rst) is
begin
if (rising_edge(clk)) then
if (RST_ASYNC_G and rst = '1') then
r <= REG_INIT_C after TPD_G;
elsif rising_edge(clk) then
r <= rin after TPD_G;
end if;
end process sync;
end process seq;

end rtl;
23 changes: 14 additions & 9 deletions protocols/sugoi/rtl/SugoiSubordinateCore.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,8 +25,10 @@ use surf.AxiLitePkg.all;

entity SugoiSubordinateCore is
generic (
TPD_G : time := 1 ns);
TPD_G : time := 1 ns;
RST_ASYNC_G : boolean := true);
port (
simRst : in sl := '0'; -- Simulation reset only
-- Clock and Reset
clk : in sl;
rst : out sl; -- Active HIGH global reset
Expand Down Expand Up @@ -73,12 +75,13 @@ begin
U_Deserializer : entity surf.Gearbox
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
SLAVE_WIDTH_G => 1,
MASTER_WIDTH_G => 10)
port map (
-- Clock and Reset
clk => clk,
rst => '0', -- Never reset on global reset command
rst => simRst, -- Simulation reset only
-- Slip Interface
slip => rxSlip,
-- Slave Interface
Expand All @@ -96,13 +99,12 @@ begin
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => '1', -- active HIGH reset
-- FLOW_CTRL_EN_G => true, -- placeholder incase FLOW_CTRL_EN_G is added in the future
RST_ASYNC_G => false,
RST_ASYNC_G => RST_ASYNC_G,
NUM_BYTES_G => 1)
port map (
-- Clock and Reset
clk => clk,
rst => '0', -- Never reset on global reset command
rst => simRst, -- Simulation reset only
-- Encoded Interface
validIn => rxEncodeValid,
dataIn => rxEncodeData,
Expand All @@ -120,8 +122,10 @@ begin
-------------
U_Fsm : entity surf.SugoiSubordinateFsm
generic map (
TPD_G => TPD_G)
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G)
port map (
simRst => simRst,
-- Clock and Reset
clk => clk,
rst => rst,
Expand Down Expand Up @@ -154,12 +158,12 @@ begin
TPD_G => TPD_G,
RST_POLARITY_G => '1', -- active HIGH reset
FLOW_CTRL_EN_G => true,
RST_ASYNC_G => false,
RST_ASYNC_G => RST_ASYNC_G,
NUM_BYTES_G => 1)
port map (
-- Clock and Reset
clk => clk,
rst => '0', -- Never reset on global reset command
rst => simRst, -- Simulation reset only
-- Decoded Interface
validIn => txDecodeValid,
dataIn => txDecodeData,
Expand All @@ -174,12 +178,13 @@ begin
U_Serializer : entity surf.Gearbox
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
SLAVE_WIDTH_G => 10,
MASTER_WIDTH_G => 1)
port map (
-- Clock and Reset
clk => clk,
rst => '0', -- Never reset on global reset command
rst => simRst, -- Simulation reset only
-- Slave Interface
slaveValid => txEncodeValid,
slaveData => txEncodeData,
Expand Down
Loading

0 comments on commit f771285

Please sign in to comment.