Some fixes for fpga/

[stefanct]

While working on porting pulpino to Vivado 2018.3 I was fixing a low-hanging problems in the build scripts within fpga/. The Makefiles of the IP cores could be made completely the same/a single file but I refrained from that for now. Also, cleaning all sub-projects on every run seems a bit silly... but I am not nearly knowledgeable enough in the context of Vivado IPs to provide a proper setup for that though. More to come when I get 2018.3 to work...

[stefanct]

Since the sw/ part relies on some outputs of the pulpemu part I'll push an update shortly that adds this dependency to the fpga/ Makefile as well.

[stefanct]

While we are at it... why are xilinx_mem_8192x32 and xilinx_mem_8192x32_dp a thing? :) AFAICT they are not used at all? Shouldn't we drop them?

[FrancescoConti]

Hi @stefanct , I think these may be removed safely. I think we can remove and merge your changes if you manage to get this working on 2018.3... unfortunately no one in the PULP team is working actively on PULPino at the moment, so we cannot help that much I'm afraid...

[stefanct]

Hi,
took me a bit longer but as a bonus there is now a script that completely automates creating the SD card ;) I have tested these with a Zedboard and Vivado 2015.1 and the led_test. It should not break any existing setups but only fix more or less annoying bugs in the fpga build flow.

[jurevreca12]

Hey,
Did you manage to port it to vivado 2018 jet?

[stefanct]

Hi,
unfortunately not but I put this effort aside for now. If you want to give it a try I suggest you build upon this since it has lots of other fixes and the last commit is a good base for the conversion. However, you will have to fix this (hopefully last) issue: #270 (comment)

Edit: one of the spiload commits had a severe bug thus I re-pushed that branch which changed the commit ID above.

[saahm]

Hi @stefanct I'm currently trying to get this repository running for Vivado 2018.3. In face before I found your pull request I tried fixing whatever errors came around.
It seems that you did more clean-up.

Yet I cannot completly build the whole project. I changed the regarding tcl scripts for compiling (setting the floating point IP to 7.1 from 7.0, removing dirs that caused errors when existing empty, etc.).

I currently get stopped by
# source tcl/ips_inc_dirs.tcl couldn't read file "tcl/ips_inc_dirs.tcl": no such file or directory while executing "source tcl/ips_inc_dirs.tcl" (file "tcl/run.tcl" line 62)
when using make all in the fpga directory. Did you already encounter these problems?

[stefanct]

On Tue, 30 Apr 2019 03:04:45 -0700 saahm ***@***.***> wrote: Hi @stefanct I'm currently trying to get this repository running for Vivado 2018.3. In face before I found your pull request I tried fixing whatever errors came around. It seems that you did more clean-up. Yet I cannot completly build the whole project. I changed the regarding tcl scripts for compiling (setting the floating point IP to 7.1 from 7.0, removing dirs that caused errors when existing empty, etc.). I currently get stopped by ` # source tcl/ips_inc_dirs.tcl couldn't read file "tcl/ips_inc_dirs.tcl": no such file or directory while executing "source tcl/ips_inc_dirs.tcl" (file "tcl/run.tcl" line 62) ` when using `make all` in the fpga directory. Did you already encounter these problems?

Hi, my guess would be a problem with the IPs repositories. Pulpino does not use ordinary git submodules but have dedicated scripts to handle/import repositories they rely on, cf. Pulpino's readme.

…

-- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

[saahm]

Hi,

that worked thanks. I checked your commits and figured out, that my changes to get it running for Vivado 2018.3 are similar (you seem to propagate more proper changes in makefiles, etc. while I just fix whatever creates an error in the tcl scripts).
Currenlty I get an error stating ERROR: [Synth 8-439] module 'ps7_axi_crossbar_0_0' not found ... while the ps7_axi_crossbar_0_0 module is available in pulpemu/pulpemu.srcs/sources_1/bd/ps7/ip/ps7_axi_crossbar_0_0/....
The error seems happen when the console outputs

Command: synth_design -rtl -name rtl_1
Starting synth_design
Using part: xc7z020clg484-1
Top: pulpemu_top

[stefanct]

Yeah, I am way too thorough (to get anything done productively ;) I remember that problem with the axi crossbar. Did you try my branch or try to recreate the changes yourself? IIRC I have fixed it but I don't remember from the top of my head what the problem was.

[saahm]

I have not tried your branch yet. I was pretty much all the way in the process of "porting" it to 2018.3 when I stumbled on your pull request.
But since you stated you figured out the problem with the axi crossbar I might be able to track it down in your commits. I will try your branch next if it that does not work out.

[saahm]

Alright, I happen to check your branch out and try your pull request changes. Sadly I encounter the axi crossbar issue as well.
I checked out your pull request and tried make all.
I encountered the version mismatch of the floating point ip (changed the version from 7.0 to 7.1 in the ips/xilinx_fp_fma/tcl/run.tcl file).
The next problem was the version mismatch between my vivado version (2018.3) and the one specified in the pulpemu/tcl/ps7_bd.tcl. After changing that one it throws the same axi crossbar error messages as on my port.
There is also a critical warning showing up close to the end stating that the clock ip manager was generated by some vivado 2017 version and might not match constraints properly (this might be an issue later if constraint files differ [which i do not expect from 2017 to 2018 when it comes to clock ip manager]).

Do you have multiple versions of vivado on your machine that it doesnt error on the fp fma or is this dependant on the linux distribution you run? I run vivado and the riscv toolchain as well as the repository and its dependencies on a clean lubuntu 16 lts for reference.

[stefanct]

I was speaking about the other branch that specifically deals with Vivado 2018.3 issues, not the more general fixes of this very pull request. Sorry for the confusion. We should probably continue in the respective issue since this one is rather for the other more general issues/improvements that work with older versions of Vivado as well.

[saahm]

Oh thanks. That truly clears up a lot of confusion. I will try out your fork. I quickly checked the diff to this repository and found files I havent touched my try of porting it. So it looks promising.

[hbhangale3]

hi @stefanct ive also started working on pulpino and using zedboard for implementation on FPGA purpose and and im constantly facing the following error could you please help me resolve it;

ERROR: [Synth 8-1766] cannot open include file config.sv [/home/U17EC115/Downloads/pulpino-master/rtl/sp_ram_wrap.sv:11]
INFO: [Synth 8-2350] module sp_ram_wrap ignored due to previous errors [/home/U17EC115/Downloads/pulpino-master/rtl/sp_ram_wrap.sv:13]
Failed to read verilog '/home/U17EC115/Downloads/pulpino-master/rtl/sp_ram_wrap.sv'

[stefanct]

Superseded.