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Some fixes for fpga/ #280

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51 changes: 22 additions & 29 deletions fpga/Makefile
Original file line number Diff line number Diff line change
@@ -1,62 +1,55 @@
all: ips pulpino pulpemu sw



# Create list of all *.dcp files based on the subdirectories of ips/
IP_OUTPUTS:=$(foreach d,$(subst ips/,,$(wildcard ips/*)),ips/$(d)/ip/$(d).dcp)
.PHONY: ips
ips: clk mem fp_fma


.PHONY: clk
clk: ips/xilinx_clock_manager/ip/xilinx_clock_manager.dcp

ips/xilinx_clock_manager/ip/xilinx_clock_manager.dcp:
make -C ips/xilinx_clock_manager/ clean all

$(MAKE) -C ips/xilinx_clock_manager/ clean all

.PHONY: mem
mem: ips/xilinx_mem_8192x32/ip/xilinx_mem_8192x32.dcp

ips/xilinx_mem_8192x32/ip/xilinx_mem_8192x32.dcp:
make -C ips/xilinx_mem_8192x32/ clean all


.PHONY: mem_dp
mem_dp: ips/xilinx_mem_32768x32_dp/ip/xilinx_mem_32768x32_dp.dcp

ips/xilinx_mem_32768x32_dp/ip/xilinx_mem_32768x32_dp.dcp:
make -C ips/xilinx_mem_32768x32_dp/ clean all
$(MAKE) -C ips/xilinx_mem_8192x32/ clean all

.PHONY: fp_fma
fp_fma: ips/xilinx_fp_fma/ip/xilinx_fp_fma.dcp

ips/xilinx_fp_fma/ip/xilinx_fp_fma.dcp:
make -C ips/xilinx_fp_fma/ clean all
$(MAKE) -C ips/xilinx_fp_fma/ clean all


.PHONY: pulpino
pulpino: pulpino/pulpino.edf
pulpino: pulpino/pulpino.edn

pulpino/pulpino.edf:
make -C pulpino clean all
pulpino/pulpino.edn: $(IP_OUTPUTS)
$(MAKE) -C pulpino clean all


.PHONY: pulpemu
pulpemu: pulpemu/pulpemu_top.bit
pulpemu: pulpemu/pulpemu_top.bit pulpemu/pulpemu_top.sysdef

pulpemu/pulpemu_top.bit:
make -C pulpemu clean all
# Only pattern rules handle multiple targets in a single recipe by
# invoking it only once cf. https://www.gnu.org/software/make/manual/html_node/Pattern-Intro.html
%emu/pulpemu_top.bit %emu/pulpemu_top.sysdef: %ino/pulpino.edn
$(MAKE) -C pulpemu clean all


.PHONY: sw
sw:
make -C sw all
sw: pulpemu/pulpemu_top.bit pulpemu/pulpemu_top.sysdef
$(MAKE) -C sw all


.PHONY: clean
clean:
make -C ips/xilinx_clock_manager/ clean
make -C ips/xilinx_mem_8192x32/ clean
make -C ips/xilinx_mem_32768x32_dp/ clean
make -C ips/xilinx_fp_fma/ clean
make -C pulpino clean
make -C pulpemu clean
make -C sw clean
$(MAKE) -C ips/xilinx_clock_manager/ clean
$(MAKE) -C ips/xilinx_mem_8192x32/ clean
$(MAKE) -C ips/xilinx_fp_fma/ clean
$(MAKE) -C pulpino clean
$(MAKE) -C pulpemu clean
$(MAKE) -C sw clean
10 changes: 9 additions & 1 deletion fpga/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ Linux running on the ARM cores of the ZYNQ.
enviornment variables XILINX_BOARD and XILINX_PART to control the board and part number.
if you don't specify these, the following defaults values are used:
XILINX_PART "xc7z020clg484-1"
XILINX_BOARD "em.avnet.com:zynq:zed:c"
XILINX_BOARD "em.avnet.com:zed:0.9"


1. Make sure you have the Vivado toolchain and the Xilinx SDK toolchain in your
Expand All @@ -66,6 +66,14 @@ Linux running on the ARM cores of the ZYNQ.
4. Prepare the SD card and the ZedBoard for booting via SD card.
To prepare the card, follow the Xilinx guide [1].

Alternatively, you can run `make install SD_DEV=/dev/your_sd_card`
in the `fpga/sw` directory. This will automatically partition the
given block device and copy the files of step 5 and 6. If `SD_DEV`
is not given `/dev/mmcblk0` will be used.
After running the script you can inspect the resulting file systems
in `/mnt/pulpino_...`. When done call `make umount` and continue with
step 7. Attention: this removes all `/mnt/pulpino_*` directories.

5. Copy the BOOT.BIN, uImage and devicetree.dtb files to the first partition of the SD card.
Those files can be found inside the `fpga/sw/sd_image` folder.

Expand Down
5 changes: 5 additions & 0 deletions fpga/common/messages.tcl → fpga/common/common.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -12,3 +12,8 @@ set_msg_config -id {[Opt 31-32]} -new_severity "info"
set_msg_config -id {[Shape Builder 18-119]} -new_severity "warning"
set_msg_config -id {[Filemgmt 20-742]} -new_severity "error"

# Set number of CPUs, default to 4 if system's getconf doesn't work
set CPUS [exec getconf _NPROCESSORS_ONLN]
if { ![info exists CPUS] } {
set CPUS 4
}
3 changes: 2 additions & 1 deletion fpga/ips/xilinx_clock_manager/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -11,13 +11,14 @@ gui:

clean:
rm -rf ip/*
mkdir -p ip
rm -rf ${PROJECT}.xpr
rm -rf ${PROJECT}.hw
rm -rf ${PROJECT}.data
rm -rf ${PROJECT}.runs
rm -rf ${PROJECT}.sim
rm -rf ${PROJECT}.srcs
rm -rf ${PROJECT}.cache
rm -rf ${PROJECT}.ip_user_files
rm -rf component.xml
rm -rf vivado*.jou
rm -rf vivado*.log
Expand Down
8 changes: 5 additions & 3 deletions fpga/ips/xilinx_clock_manager/tcl/run.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -4,16 +4,18 @@ if { ![info exists ::env(XILINX_PART)] } {
}

if { ![info exists ::env(XILINX_BOARD)] } {
set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c"
set ::env(XILINX_BOARD) "em.avnet.com:zed:0.9"
}

source ../../common/common.tcl

set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)

set ila_name xilinx_clock_manager

create_project $ila_name . -part $partNumber
set_property board $boardName [current_project]
set_property board_part $boardName [current_project]

create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ila_name

Expand All @@ -24,6 +26,6 @@ set_property -dict [list CONFIG.INTERFACE_SELECTION {Enable_AXI} CONFIG.USE_DYN_
generate_target {instantiation_template} [get_files ./$ila_name.srcs/sources_1/ip/$ila_name/$ila_name.xci]
generate_target all [get_files ./$ila_name.srcs/sources_1/ip/$ila_name/$ila_name.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ila_name.srcs/sources_1/ip/$ila_name/$ila_name.xci]
launch_run -jobs 8 ${ila_name}_synth_1
launch_run -jobs $CPUS ${ila_name}_synth_1
wait_on_run ${ila_name}_synth_1

3 changes: 2 additions & 1 deletion fpga/ips/xilinx_fp_fma/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,14 @@ gui:

clean:
rm -rf ip/*
mkdir -p ip
rm -rf ${PROJECT}.xpr
rm -rf ${PROJECT}.hw
rm -rf ${PROJECT}.data
rm -rf ${PROJECT}.runs
rm -rf ${PROJECT}.sim
rm -rf ${PROJECT}.srcs
rm -rf ${PROJECT}.cache
rm -rf ${PROJECT}.ip_user_files
rm -rf component.xml
rm -rf vivado*.jou
rm -rf vivado*.log
Expand Down
8 changes: 5 additions & 3 deletions fpga/ips/xilinx_fp_fma/tcl/run.tcl
100755 → 100644
Original file line number Diff line number Diff line change
Expand Up @@ -4,17 +4,19 @@ if { ![info exists ::env(XILINX_PART)] } {
}

if { ![info exists ::env(XILINX_BOARD)] } {
set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c"
set ::env(XILINX_BOARD) "em.avnet.com:zed:0.9"
}

source ../../common/common.tcl

set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)

create_project xilinx_fp_fma . -part $partNumber
set_property board $boardName [current_project]
set_property board_part $boardName [current_project]
create_ip -name floating_point -vendor xilinx.com -library ip -version 7.0 -module_name xilinx_fp_fma
set_property -dict [list CONFIG.Operation_Type {FMA} CONFIG.Flow_Control {NonBlocking} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Has_RESULT_TREADY {false} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETn {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {Medium_Usage} CONFIG.C_Latency {2} CONFIG.C_Rate {1}] [get_ips xilinx_fp_fma]
generate_target all [get_files ./xilinx_fp_fma.srcs/sources_1/ip/xilinx_fp_fma/xilinx_fp_fma.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./xilinx_fp_fma.srcs/sources_1/ip/xilinx_fp_fma/xilinx_fp_fma.xci]
launch_run -jobs 8 xilinx_fp_fma_synth_1
launch_run -jobs $CPUS xilinx_fp_fma_synth_1
wait_on_run xilinx_fp_fma_synth_1
10 changes: 0 additions & 10 deletions fpga/ips/xilinx_mem_32768x32/.gitignore

This file was deleted.

28 changes: 0 additions & 28 deletions fpga/ips/xilinx_mem_32768x32/Makefile

This file was deleted.

20 changes: 0 additions & 20 deletions fpga/ips/xilinx_mem_32768x32/tcl/run.tcl

This file was deleted.

10 changes: 0 additions & 10 deletions fpga/ips/xilinx_mem_32768x32_dp/.gitignore

This file was deleted.

27 changes: 0 additions & 27 deletions fpga/ips/xilinx_mem_32768x32_dp/Makefile

This file was deleted.

20 changes: 0 additions & 20 deletions fpga/ips/xilinx_mem_32768x32_dp/tcl/run.tcl

This file was deleted.

3 changes: 2 additions & 1 deletion fpga/ips/xilinx_mem_8192x32/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -13,13 +13,14 @@ gui:

clean:
rm -rf ip/*
mkdir -p ip
rm -rf ${PROJECT}.xpr
rm -rf ${PROJECT}.hw
rm -rf ${PROJECT}.data
rm -rf ${PROJECT}.runs
rm -rf ${PROJECT}.sim
rm -rf ${PROJECT}.srcs
rm -rf ${PROJECT}.cache
rm -rf ${PROJECT}.ip_user_files
rm -rf component.xml
rm -rf vivado*.jou
rm -rf vivado*.log
Expand Down
8 changes: 5 additions & 3 deletions fpga/ips/xilinx_mem_8192x32/tcl/run.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -4,17 +4,19 @@ if { ![info exists ::env(XILINX_PART)] } {
}

if { ![info exists ::env(XILINX_BOARD)] } {
set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c"
set ::env(XILINX_BOARD) "em.avnet.com:zed:0.9"
}

source ../../common/common.tcl

set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)

create_project xilinx_mem_8192x32 . -part $partNumber
set_property board $boardName [current_project]
set_property board_part $boardName [current_project]
create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name xilinx_mem_8192x32
set_property -dict [list CONFIG.Memory_Type {Single_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {8192} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Use_RSTA_Pin {true}] [get_ips xilinx_mem_8192x32]
generate_target all [get_files ./xilinx_mem_8192x32.srcs/sources_1/ip/xilinx_mem_8192x32/xilinx_mem_8192x32.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./xilinx_mem_8192x32.srcs/sources_1/ip/xilinx_mem_8192x32/xilinx_mem_8192x32.xci]
launch_run -jobs 8 xilinx_mem_8192x32_synth_1
launch_run -jobs $CPUS xilinx_mem_8192x32_synth_1
wait_on_run xilinx_mem_8192x32_synth_1
3 changes: 2 additions & 1 deletion fpga/pulpemu/.gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -11,4 +11,5 @@ vivado*.backup.log
*.hwdef
*.txt
.Xil
pulpemu_top.bit
pulpemu_top.bit
pulpemu_top.sysdef
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