fpga: fix board selection

- Set default board name to em.avnet.com:zed:0.9 This corresponds to revision C of the Zedboard since at least Vivado 2015.1. - Use "board_part" property instead of just "board" as suggested by Vivado 2015.1.
pulp-platform · Feb 13, 2019 · 4c26d68 · 4c26d68
1 parent b5ab1e3
commit 4c26d68
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Showing 8 changed files with 14 additions and 14 deletions.
diff --git a/fpga/README.md b/fpga/README.md
@@ -44,7 +44,7 @@ Linux running on the ARM cores of the ZYNQ.
    enviornment variables XILINX_BOARD and XILINX_PART to control the board and part number.
    if you don't specify these, the following defaults values are used:
    XILINX_PART "xc7z020clg484-1"
-   XILINX_BOARD "em.avnet.com:zynq:zed:c"
+   XILINX_BOARD "em.avnet.com:zed:0.9"
 
 
 1. Make sure you have the Vivado toolchain and the Xilinx SDK toolchain in your

diff --git a/fpga/ips/xilinx_clock_manager/tcl/run.tcl b/fpga/ips/xilinx_clock_manager/tcl/run.tcl
@@ -4,7 +4,7 @@ if { ![info exists ::env(XILINX_PART)] } {
 }
 
 if { ![info exists ::env(XILINX_BOARD)] } {
-  set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c"
+  set ::env(XILINX_BOARD) "em.avnet.com:zed:0.9"
 }
 
 source ../../common/common.tcl
@@ -15,7 +15,7 @@ set boardName  $::env(XILINX_BOARD)
 set ila_name xilinx_clock_manager
 
 create_project $ila_name . -part $partNumber
-set_property board $boardName [current_project]
+set_property board_part $boardName [current_project]
 
 create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ila_name
 

diff --git a/fpga/ips/xilinx_fp_fma/tcl/run.tcl b/fpga/ips/xilinx_fp_fma/tcl/run.tcl
@@ -4,7 +4,7 @@ if { ![info exists ::env(XILINX_PART)] } {
 }
 
 if { ![info exists ::env(XILINX_BOARD)] } {
-  set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c"
+  set ::env(XILINX_BOARD) "em.avnet.com:zed:0.9"
 }
 
 source ../../common/common.tcl
@@ -13,7 +13,7 @@ set partNumber $::env(XILINX_PART)
 set boardName  $::env(XILINX_BOARD)
 
 create_project xilinx_fp_fma . -part $partNumber
-set_property board $boardName [current_project]
+set_property board_part $boardName [current_project]
 create_ip -name floating_point -vendor xilinx.com -library ip -version 7.0 -module_name xilinx_fp_fma
 set_property -dict [list CONFIG.Operation_Type {FMA} CONFIG.Flow_Control {NonBlocking} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Has_RESULT_TREADY {false} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETn {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {Medium_Usage} CONFIG.C_Latency {2} CONFIG.C_Rate {1}] [get_ips xilinx_fp_fma]
 generate_target all [get_files ./xilinx_fp_fma.srcs/sources_1/ip/xilinx_fp_fma/xilinx_fp_fma.xci]

diff --git a/fpga/ips/xilinx_mem_32768x32/tcl/run.tcl b/fpga/ips/xilinx_mem_32768x32/tcl/run.tcl
@@ -4,7 +4,7 @@ if { ![info exists ::env(XILINX_PART)] } {
 }
 
 if { ![info exists ::env(XILINX_BOARD)] } {
-  set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c"
+  set ::env(XILINX_BOARD) "em.avnet.com:zed:0.9"
 }
 
 source ../../common/common.tcl
@@ -13,7 +13,7 @@ set partNumber $::env(XILINX_PART)
 set boardName  $::env(XILINX_BOARD)
 
 create_project xilinx_mem_32768x32 . -part $partNumber
-set_property board $boardName [current_project]
+set_property board_part $boardName [current_project]
 create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name xilinx_mem_32768x32
 set_property -dict [list CONFIG.Memory_Type {Single_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {32768} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Use_RSTA_Pin {true}] [get_ips xilinx_mem_32768x32]
 generate_target all [get_files ./xilinx_mem_32768x32.srcs/sources_1/ip/xilinx_mem_32768x32/xilinx_mem_32768x32.xci]

diff --git a/fpga/ips/xilinx_mem_32768x32_dp/tcl/run.tcl b/fpga/ips/xilinx_mem_32768x32_dp/tcl/run.tcl
@@ -4,7 +4,7 @@ if { ![info exists ::env(XILINX_PART)] } {
 }
 
 if { ![info exists ::env(XILINX_BOARD)] } {
-  set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c"
+  set ::env(XILINX_BOARD) "em.avnet.com:zed:0.9"
 }
 
 source ../../common/common.tcl
@@ -13,7 +13,7 @@ set partNumber $::env(XILINX_PART)
 set boardName  $::env(XILINX_BOARD)
 
 create_project xilinx_mem_32768x32_dp . -part $partNumber
-set_property board $boardName [current_project]
+set_property board_part $boardName [current_project]
 create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name xilinx_mem_32768x32_dp
 set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {32768} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Core {false} CONFIG.Use_RSTA_Pin {true} CONFIG.Use_RSTB_Pin {true}] [get_ips xilinx_mem_32768x32_dp]
 generate_target all [get_files ./xilinx_mem_32768x32_dp.srcs/sources_1/ip/xilinx_mem_32768x32_dp/xilinx_mem_32768x32_dp.xci]

diff --git a/fpga/ips/xilinx_mem_8192x32/tcl/run.tcl b/fpga/ips/xilinx_mem_8192x32/tcl/run.tcl
@@ -4,7 +4,7 @@ if { ![info exists ::env(XILINX_PART)] } {
 }
 
 if { ![info exists ::env(XILINX_BOARD)] } {
-  set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c"
+  set ::env(XILINX_BOARD) "em.avnet.com:zed:0.9"
 }
 
 source ../../common/common.tcl
@@ -13,7 +13,7 @@ set partNumber $::env(XILINX_PART)
 set boardName  $::env(XILINX_BOARD)
 
 create_project xilinx_mem_8192x32 . -part $partNumber
-set_property board $boardName [current_project]
+set_property board_part $boardName [current_project]
 create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name xilinx_mem_8192x32
 set_property -dict [list CONFIG.Memory_Type {Single_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {8192} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Use_RSTA_Pin {true}] [get_ips xilinx_mem_8192x32]
 generate_target all [get_files ./xilinx_mem_8192x32.srcs/sources_1/ip/xilinx_mem_8192x32/xilinx_mem_8192x32.xci]

diff --git a/fpga/pulpemu/tcl/run.tcl b/fpga/pulpemu/tcl/run.tcl
@@ -10,7 +10,7 @@ if { ![info exists ::env(XILINX_PART)] } {
     set ::env(XILINX_PART) "xc7z020clg484-1"
 
     if { ![info exists ::env(XILINX_BOARD)] } {
-      set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c"
+      set ::env(XILINX_BOARD) "em.avnet.com:zed:0.9"
     }
   }
 }
@@ -39,7 +39,7 @@ set FPGA_PULPINO ../pulpino
 create_project pulpemu . -part $::env(XILINX_PART)
 
 if { [info exists ::env(XILINX_BOARD) ] } {
-  set_property board $::env(XILINX_BOARD) [current_project]
+  set_property board_part $::env(XILINX_BOARD) [current_project]
 }
 
 

diff --git a/fpga/pulpino/tcl/run.tcl b/fpga/pulpino/tcl/run.tcl
@@ -7,7 +7,7 @@ if { ![info exists ::env(XILINX_PART)] } {
 }
 
 if { ![info exists ::env(XILINX_BOARD)] } {
-  set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c"
+  set ::env(XILINX_BOARD) "em.avnet.com:zed:0.9"
 }
 
 if { ![info exists ::env(USE_ZERO_RISCY)] } {