Tiled Memory Support

Data of 2 or more dimensions is typically mapped to addresses by mappings such as baseAddress + elemSize*(rowNum*colDim + colNum). In such a linear mapping, vertically adjacent elements differ in address by pitch = colDim*elemsize. If the pitch exceeds the cache line size, vertically adjacent elements lie in separate cache lines. If the pitch exceeds the virtual memory page size vertically adjacent elements lie in separate pages.

Algorithms processing such data typically operate in a neighborhood