-
Notifications
You must be signed in to change notification settings - Fork 0
Home
Welcome to the born-again comp-arch.net wiki! ... Save the applause until fully resuscitated.
2023-06-19: Not making much progress at all.
2021: In these early days of the resuscitation, the pages will be collected essentially randomly. Eventually I will restore the original hierarchy of pages, and hopefully improve it by automation (which should be easier nowadays since I am using the git wiki with text files rather than MediaWiki).
2023-06-19: Picking up again after a lapse of >2 years?
- date written or updated
-
-
Performance Monitoring Hardware Design Issues for Dynamically Scheduled Processors, 1998
- TBD: Overall discussion of Performance Monitoring Hardware, EMON
- Event Counting, Interrupt Based Statistical Profiling, Longitudinal Profiling
- Last Branch Records (LBRs)
- etc.
-
Original MLP Memory Level Parallelism presentation at ASPLOS WACI 1998
- TBD: overall discussion of MLP Memory Level Parallelism
-
Coherent Threading and Dynamic GPUs, including the 2009 Berkeley ParLab presentation
- TBD: overall discussion of Dynamic GPU architecture
- TBD: architectures to REDUCE parallelism
-
LAVI: Loop around Variable Instruction - an ISA pattern
Interrupts, Exceptions, Traps... Cross-Domain Calls and RPC
Store Coherence and Cache Flush Coherence
CMOs - Cache Management Operations
Here or There - personal GitHub versus RISC-V GitHub
Capabilities with and without Special Tagged Memory - 2020-11-16
Atomics vs Load Linked & Store Conditional (LL & SC)
Conditional Select, Move, Merge branchless instructions
There will always be a need for one more privilege level
Large pages via Contiguous PTEs and partial occupancy
- Convert to Specified Endianness
- Byte Address Invariant Endianness versus Word Data Value Invariant Endianness
- Endianness means that Packed Vector ISAs must specify Element Width
Negative Offsets, Indexes, and Counters
Breaking out of the RISC 3-register, 2-input 1-output straitjacket