Skip to content

Issues: verilog-to-routing/vtr-verilog-to-routing

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort

Issues list

[Prepacker] Pack Molecule Data Structure Clarity
#2791 opened Oct 30, 2024 by AlexandreSinger
1 of 9 tasks
[IntraClusterPlacement] Code Cleanups
#2732 opened Sep 20, 2024 by AlexandreSinger
1 of 4 tasks
[Packer] Load The ClusteredNetlist Directly From The ClusterLegalizer VPR VPR FPGA Placement & Routing Tool
#2731 opened Sep 20, 2024 by AlexandreSinger
[ClusterLegalizer] Code Cleanups VPR VPR FPGA Placement & Routing Tool
#2730 opened Sep 20, 2024 by AlexandreSinger
6 tasks
[Packer] Setting Higher Target Pin Utilization When Regions are Full VPR VPR FPGA Placement & Routing Tool
#2729 opened Sep 20, 2024 by AlexandreSinger
CLBs Positioned Far from IOs
#2727 opened Sep 17, 2024 by WindFrank
Multibit Adder Architecture Failure
#2717 opened Sep 9, 2024 by shrekliao
ProTip! Follow long discussions with comments:>50.