20170905 Release with Alan's 20.480Mhz fix

softerhardware · Sep 6, 2017 · cd978be · cd978be
1 parent e4673c4
commit cd978be
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Showing 2 changed files with 23 additions and 11 deletions.
diff --git a/firmware/hermeslite.qpf b/firmware/hermeslite.qpf
@@ -19,15 +19,15 @@
 #
 # Quartus Prime
 # Version 16.1.2 Build 203 01/18/2017 SJ Lite Edition
-# Date created = 18:06:28  September 04, 2017
+# Date created = 20:42:07  September 05, 2017
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "16.1"
-DATE = "18:06:28  September 04, 2017"
+DATE = "20:42:07  September 05, 2017"
 
 # Revisions
 
-PROJECT_REVISION = "beta2"
 PROJECT_REVISION = "beta3"
+PROJECT_REVISION = "beta2"
 PROJECT_REVISION = "hermeslite"
diff --git a/firmware/rtl/cordic.v b/firmware/rtl/cordic.v
@@ -27,11 +27,11 @@ Boston, MA  02110-1301, USA.
 module cordic( clock, frequency, in_data, out_data_I, out_data_Q );
 
 parameter IN_WIDTH   = 12; //ADC bitwidth
-parameter EXTRA_BITS = 5;  //spur reduction 6 dB per bit
+parameter EXTRA_BITS = 6;  //spur reduction 6 dB per bit
 
 //internal params
 localparam WR =  IN_WIDTH + EXTRA_BITS + 1; //18-bit data regs
-localparam OUT_WIDTH = WR;                  //18-bit output width
+localparam OUT_WIDTH = 18;                  //18-bit output width
 localparam WZ =  IN_WIDTH + EXTRA_BITS - 1; //16-bit angle regs
 localparam STG = IN_WIDTH + EXTRA_BITS - 2; //15 stages
 localparam WO = OUT_WIDTH;
@@ -195,17 +195,29 @@ generate
 
   else
     begin
-    reg signed [WO-1:0] rounded_I = 0;
-    reg signed [WO-1:0] rounded_Q = 0;
+    reg signed [WR-1:0] rounded_I = 0;
+    reg signed [WR-1:0] rounded_Q = 0;
 
     always @(posedge clock)
       begin
-      rounded_I <= X[STG-1][WR-1 : WR-WO] + X[STG-1][WR-1-WO];
-      rounded_Q <= Y[STG-1][WR-1 : WR-WO] + Y[STG-1][WR-1-WO];
+   //   rounded_I <= X[STG-1][WR-1 : WR-WO] +{{(WO-1){1'b0}},  X[STG-1][WR-1-WO]};
+   //   rounded_Q <= Y[STG-1][WR-1 : WR-WO] +{{(WO-1){1'b0}},   Y[STG-1][WR-1-WO]};
+   // rounding from http://zipcpu.com/dsp/2017/07/22/rounding.html
+     rounded_I <= X[STG-1][WR-1 :0]
+							+ {{(WO){1'b0}},
+							X[STG-1][WR-WO],
+							{(WR-WO-1){!X[STG-1][WR-WO]}}};
+
+		rounded_Q <= Y[STG-1][WR-1 :0]
+							+ {{(WO){1'b0}},
+							Y[STG-1][WR-WO],
+							{(WR-WO-1){!Y[STG-1][WR-WO]}}};
+
+
       end
 
-    assign out_data_I = rounded_I;
-    assign out_data_Q = rounded_Q;
+    assign out_data_I = rounded_I[WR-1:WR-WO];
+    assign out_data_Q = rounded_Q[WR-1:WR-WO];
     end
 endgenerate