Beta3 switch to 3.3V LEDs, fix for 20.480MHz spur, 20170904 release

firmware/ethernet/mdio.v

@@ -47,8 +47,14 @@ module mdio(
 
 
 //bits to send
+`ifdef BETA3
+wire [63:0] wr_bits = {32'hFFFFFFFF, 9'b010100111, addr, 2'b10, wr_data};  // PHYAD[4:0]=5'h7
+wire [63:0] rd_bits = {32'hFFFFFFFF, 9'b011000111, addr, 2'bxx, 16'hFFFF}; // PHYAD[4:0]=5'h7
+`else
 wire [63:0] wr_bits = {32'hFFFFFFFF, 9'b010100100, addr, 2'b10, wr_data};
 wire [63:0] rd_bits = {32'hFFFFFFFF, 9'b011000100, addr, 2'bxx, 16'hFFFF};
+`endif
+
 reg[ 5:0] bit_no;
 
 

firmware/hermeslite.qpf

@@ -19,15 +19,15 @@
 #
 # Quartus Prime
 # Version 16.1.2 Build 203 01/18/2017 SJ Lite Edition
-# Date created = 21:33:20  July 31, 2017
+# Date created = 18:06:28  September 04, 2017
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "16.1"
-DATE = "21:33:20  July 31, 2017"
+DATE = "18:06:28  September 04, 2017"
 
 # Revisions
 
-PROJECT_REVISION = "beta3"
 PROJECT_REVISION = "beta2"
+PROJECT_REVISION = "beta3"
 PROJECT_REVISION = "hermeslite"

firmware/rtl/hermeslite.v

@@ -338,7 +338,7 @@ ethernet #(.MAC(MAC), .IP(IP), .Hermes_serialno(Hermes_serialno)) ethernet_inst
     // Status
     .this_MAC_o(this_MAC),
     .run_o(run),
-    .dipsw_i({1'b0,io_cn9}),
+    .dipsw_i({io_cn10,io_cn9}),
     .AssignNR(AssignNR),
 
     // MII Ethernet PHY
@@ -1699,12 +1699,13 @@ assign pwr_envbias = FPGA_PTT & IF_PA_enable;
 assign pwr_envop = FPGA_PTT;
 assign pa_exttr = FPGA_PTT;
 assign pa_inttr = FPGA_PTT & (IF_PA_enable | ~IF_TR_disable);
+assign pwr_envpa = FPGA_PTT & IF_PA_enable;
 `else
 assign pa_tr = FPGA_PTT & (IF_PA_enable | ~IF_TR_disable);
 assign pa_en = FPGA_PTT & IF_PA_enable;
+assign pwr_envpa = FPGA_PTT;
 `endif
 
-assign pwr_envpa = FPGA_PTT & IF_PA_enable;
 assign rffe_rfsw_sel = IF_PA_enable;
 
 wire scl1_i, scl1_t, scl1_o, sda1_i, sda1_t, sda1_o;