Release Candidate v2.51.0

axi/axi-stream/rtl/AxiStreamDeMux.vhd

@@ -26,6 +26,7 @@ use surf.AxiStreamPkg.all;
 entity AxiStreamDeMux is
    generic (
       TPD_G          : time                   := 1 ns;
+      RST_POLARITY_G : sl                     := '1';    -- '1' for active HIGH reset, '0' for active LOW reset
       RST_ASYNC_G    : boolean                := false;
       NUM_MASTERS_G  : integer range 1 to 256 := 12;
       MODE_G         : string                 := "INDEXED";  -- Or "ROUTED" Or "DYNAMIC"
@@ -39,7 +40,7 @@ entity AxiStreamDeMux is
       axisRst           : in  sl;
       -- Dynamic Route Table (only used when MODE_G = "DYNAMIC")
       dynamicRouteMasks : in  slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
-      dynamicRouteDests  : in  slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
+      dynamicRouteDests : in  slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
       -- Slave
       sAxisMaster       : in  AxiStreamMasterType;
       sAxisSlave        : out AxiStreamSlaveType;
@@ -139,7 +140,7 @@ begin
       sAxisSlave <= v.slave;
 
       -- Reset
-      if (RST_ASYNC_G = false and axisRst = '1') then
+      if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
          v := REG_INIT_C;
       end if;
 
@@ -151,14 +152,14 @@ begin
 
    end process comb;
 
-   GEN_VEC :
-   for i in (NUM_MASTERS_G-1) downto 0 generate
+   GEN_VEC : for i in (NUM_MASTERS_G-1) downto 0 generate
 
       U_Pipeline : entity surf.AxiStreamPipeline
          generic map (
-            TPD_G         => TPD_G,
-            RST_ASYNC_G   => RST_ASYNC_G,
-            PIPE_STAGES_G => PIPE_STAGES_G)
+            TPD_G          => TPD_G,
+            RST_POLARITY_G => RST_POLARITY_G,
+            RST_ASYNC_G    => RST_ASYNC_G,
+            PIPE_STAGES_G  => PIPE_STAGES_G)
          port map (
             axisClk     => axisClk,
             axisRst     => axisRst,
@@ -171,7 +172,7 @@ begin
 
    seq : process (axisClk, axisRst) is
    begin
-      if (RST_ASYNC_G and axisRst = '1') then
+      if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then
          r <= REG_INIT_C after TPD_G;
       elsif rising_edge(axisClk) then
          r <= rin after TPD_G;

axi/axi-stream/rtl/AxiStreamMux.vhd

@@ -27,6 +27,7 @@ use surf.AxiStreamPkg.all;
 entity AxiStreamMux is
    generic (
       TPD_G                : time                    := 1 ns;
+      RST_POLARITY_G       : sl                      := '1';    -- '1' for active HIGH reset, '0' for active LOW reset
       RST_ASYNC_G          : boolean                 := false;
       PIPE_STAGES_G        : integer range 0 to 16   := 0;
       NUM_SLAVES_G         : integer range 1 to 256  := 4;
@@ -308,7 +309,7 @@ begin
       sAxisSlaves <= v.slaves;
 
       -- Reset
-      if (RST_ASYNC_G = false and axisRst = '1') then
+      if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
          v := REG_INIT_C;
       end if;
 
@@ -322,7 +323,7 @@ begin
 
    seq : process (axisClk, axisRst) is
    begin
-      if (RST_ASYNC_G) and (axisRst = '1') then
+      if (RST_ASYNC_G) and (axisRst = RST_POLARITY_G) then
          r <= REG_INIT_C after TPD_G;
       elsif rising_edge(axisClk) then
          r <= rin after TPD_G;
@@ -332,9 +333,10 @@ begin
    -- Optional output pipeline registers to ease timing
    AxiStreamPipeline_1 : entity surf.AxiStreamPipeline
       generic map (
-         TPD_G         => TPD_G,
-         RST_ASYNC_G   => RST_ASYNC_G,
-         PIPE_STAGES_G => PIPE_STAGES_G)
+         TPD_G          => TPD_G,
+         RST_POLARITY_G => RST_POLARITY_G,
+         RST_ASYNC_G    => RST_ASYNC_G,
+         PIPE_STAGES_G  => PIPE_STAGES_G)
       port map (
          axisClk     => axisClk,
          axisRst     => axisRst,

axi/axi-stream/rtl/AxiStreamPipeline.vhd

@@ -23,6 +23,7 @@ use surf.AxiStreamPkg.all;
 entity AxiStreamPipeline is
    generic (
       TPD_G             : time     := 1 ns;
+      RST_POLARITY_G    : sl       := '1';    -- '1' for active HIGH reset, '0' for active LOW reset
       RST_ASYNC_G       : boolean  := false;
       SIDE_BAND_WIDTH_G : positive := 1;  -- General purpose sideband
       PIPE_STAGES_G     : natural  := 0);
@@ -148,7 +149,7 @@ begin
          mSideBand   <= r.mSideBand(PIPE_STAGES_C);
 
          -- Synchronous Reset
-         if (RST_ASYNC_G = false and axisRst = '1') then
+         if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
             v := REG_INIT_C;
          end if;
 
@@ -159,7 +160,7 @@ begin
 
       seq : process (axisClk, axisRst) is
       begin
-         if (RST_ASYNC_G and axisRst = '1') then
+         if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then
             r <= REG_INIT_C after TPD_G;
          elsif rising_edge(axisClk) then
             r <= rin after TPD_G;

base/crc/rtl/Crc32.vhd

@@ -34,15 +34,16 @@ use surf.CrcPkg.all;
 entity Crc32 is
    generic (
       TPD_G            : time             := 1 ns;
+      RST_POLARITY_G   : sl               := '1';  -- '1' for active HIGH reset, '0' for active LOW reset
       RST_ASYNC_G      : boolean          := false;
       BYTE_WIDTH_G     : positive         := 4;
       INPUT_REGISTER_G : boolean          := true;
       CRC_INIT_G       : slv(31 downto 0) := x"FFFFFFFF";
       CRC_POLY_G       : slv(31 downto 0) := x"04C11DB7");
    port (
-      crcPwrOnRst  : in  sl := '0';
-      crcOut       : out slv(31 downto 0);  -- CRC output
-      crcRem       : out slv(31 downto 0);  -- CRC interim remainder
+      crcPwrOnRst  : in  sl               := not RST_POLARITY_G;
+      crcOut       : out slv(31 downto 0);         -- CRC output
+      crcRem       : out slv(31 downto 0);         -- CRC interim remainder
       crcClk       : in  sl;            -- system clock
       crcDataValid : in  sl;  -- indicate that new data arrived and CRC can be computed
       crcDataWidth : in  slv(2 downto 0);  -- indicate width in bytes minus 1, 0 - 1 byte, 1 - 2 bytes ... , 7 - 8 bytes
@@ -146,10 +147,10 @@ begin
 
    seq : process (crcClk, crcPwrOnRst) is
    begin
-      if (RST_ASYNC_G and crcPwrOnRst = '1') then
+      if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then
          r <= REG_INIT_C after TPD_G;
-      elsif  (rising_edge(crcClk)) then
-         if (RST_ASYNC_G = false and crcPwrOnRst = '1') then
+      elsif (rising_edge(crcClk)) then
+         if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then
             r <= REG_INIT_C after TPD_G;
          else
             r <= rin after TPD_G;

base/crc/rtl/Crc32Parallel.vhd

@@ -40,20 +40,21 @@ use surf.CrcPkg.all;
 entity Crc32Parallel is
    generic (
       TPD_G            : time             := 1 ns;
+      RST_POLARITY_G   : sl               := '1';  -- '1' for active HIGH reset, '0' for active LOW reset
       RST_ASYNC_G      : boolean          := false;
       BYTE_WIDTH_G     : positive         := 4;
       INPUT_REGISTER_G : boolean          := true;
       CRC_INIT_G       : slv(31 downto 0) := x"FFFFFFFF");
    port (
-      crcPwrOnRst  : in  sl := '0';
-      crcOut       : out slv(31 downto 0);  -- CRC output
-      crcRem       : out slv(31 downto 0);  -- CRC interim remainder
+      crcPwrOnRst  : in  sl               := not RST_POLARITY_G;
+      crcOut       : out slv(31 downto 0);         -- CRC output
+      crcRem       : out slv(31 downto 0);         -- CRC interim remainder
       crcClk       : in  sl;            -- system clock
       crcDataValid : in  sl;  -- indicate that new data arrived and CRC can be computed
       crcDataWidth : in  slv(2 downto 0);  -- indicate width in bytes minus 1, 0 - 1 byte, 1 - 2 bytes ... , 7 - 8 bytes
       crcIn        : in  slv((BYTE_WIDTH_G*8-1) downto 0);  -- input data for CRC calculation
       crcInit      : in  slv(31 downto 0) := CRC_INIT_G;  -- optional override of CRC_INIT_G
-      crcReset     : in  sl);  -- initializes CRC logic to crcInit
+      crcReset     : in  sl);           -- initializes CRC logic to crcInit
 end Crc32Parallel;
 
 architecture rtl of Crc32Parallel is
@@ -188,10 +189,10 @@ begin
 
    seq : process (crcClk, crcPwrOnRst) is
    begin
-      if (RST_ASYNC_G and crcPwrOnRst = '1') then
+      if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then
          r <= REG_INIT_C after TPD_G;
-      elsif  (rising_edge(crcClk)) then
-         if (RST_ASYNC_G = false and crcPwrOnRst = '1') then
+      elsif (rising_edge(crcClk)) then
+         if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then
             r <= REG_INIT_C after TPD_G;
          else
             r <= rin after TPD_G;

base/general/rtl/Scrambler.vhd

@@ -25,6 +25,7 @@ use surf.StdRtlPkg.all;
 entity Scrambler is
    generic (
       TPD_G             : time         := 1 ns;
+      RST_POLARITY_G    : sl           := '1';    -- '1' for active HIGH reset, '0' for active LOW reset
       RST_ASYNC_G       : boolean      := false;
       DIRECTION_G       : string       := "SCRAMBLER";  -- or DESCRAMBLER
       DATA_WIDTH_G      : integer      := 64;
@@ -129,7 +130,7 @@ begin
       inputReady <= v.inputReady;
 
       -- Reset
-      if (RST_ASYNC_G = false and rst = '1') then
+      if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then
          v := REG_INIT_C;
       end if;
 
@@ -150,7 +151,7 @@ begin
 
    seq : process (clk, rst) is
    begin
-      if (RST_ASYNC_G and rst = '1') then
+      if (RST_ASYNC_G and rst = RST_POLARITY_G) then
          r <= REG_INIT_C after TPD_G;
       elsif rising_edge(clk) then
          r <= rin after TPD_G;

base/sync/rtl/RstSync.vhd

@@ -4,6 +4,9 @@
 -- Description: Synchronizes the trailing edge of an asynchronous reset to a
 --              given clock.
 -------------------------------------------------------------------------------
+-- Note: Using "std_logic" instead of "sl" for generics due to issues with
+--       SystemVerilog handling VHDL subtype on generics properly
+-------------------------------------------------------------------------------
 -- This file is part of 'SLAC Firmware Standard Library'.
 -- It is subject to the license terms in the LICENSE.txt file found in the
 -- top-level directory of this distribution and at:
@@ -21,9 +24,9 @@ use surf.StdRtlPkg.all;
 
 entity RstSync is
    generic (
-      TPD_G           : time                             := 1 ns;   -- Simulation FF output delay
-      IN_POLARITY_G   : sl                               := '1';  -- 0 for active low rst, 1 for high
-      OUT_POLARITY_G  : sl                               := '1';
+      TPD_G           : time                             := 1 ns;  -- Simulation FF output delay
+      IN_POLARITY_G   : std_logic                        := '1';  -- 0 for active low rst, 1 for high
+      OUT_POLARITY_G  : std_logic                        := '1';
       BYPASS_SYNC_G   : boolean                          := false;  -- Bypass Synchronizer module for synchronous data configuration
       RELEASE_DELAY_G : integer range 3 to positive'high := 3;  -- Delay between deassertion of async and sync resets
       OUT_REG_RST_G   : boolean                          := true);  -- Apply async reset to final reg stage
@@ -57,7 +60,7 @@ begin
          dataOut => syncInt);
 
    -- Final stage does not have async constraints applied, can be duplicated to ease timing
-   OUT_REG : process (clk, asyncRst) is
+   OUT_REG : process (asyncRst, clk) is
    begin
       if (asyncRst = IN_POLARITY_G and OUT_REG_RST_G) then
          syncRst <= OUT_POLARITY_G after TPD_G;

base/sync/rtl/SynchronizerFifo.vhd

@@ -22,18 +22,19 @@ use surf.StdRtlPkg.all;
 
 entity SynchronizerFifo is
    generic (
-      TPD_G         : time                       := 1 ns;
-      RST_ASYNC_G   : boolean                    := false;
-      COMMON_CLK_G  : boolean                    := false;  -- Bypass FifoAsync module for synchronous data configuration
-      MEMORY_TYPE_G : string                     := "distributed";
-      SYNC_STAGES_G : integer range 3 to (2**24) := 3;
-      PIPE_STAGES_G : natural range 0 to 16      := 0;
-      DATA_WIDTH_G  : integer range 1 to (2**24) := 16;
-      ADDR_WIDTH_G  : integer range 2 to 48      := 4;
-      INIT_G        : slv                        := "0");
+      TPD_G          : time                       := 1 ns;
+      RST_POLARITY_G : sl                         := '1';  -- '1' for active HIGH reset, '0' for active LOW reset
+      RST_ASYNC_G    : boolean                    := false;
+      COMMON_CLK_G   : boolean                    := false;  -- Bypass FifoAsync module for synchronous data configuration
+      MEMORY_TYPE_G  : string                     := "distributed";
+      SYNC_STAGES_G  : integer range 3 to (2**24) := 3;
+      PIPE_STAGES_G  : natural range 0 to 16      := 0;
+      DATA_WIDTH_G   : integer range 1 to (2**24) := 16;
+      ADDR_WIDTH_G   : integer range 2 to 48      := 4;
+      INIT_G         : slv                        := "0");
    port (
       -- Asynchronous Reset
-      rst    : in  sl := '0';
+      rst    : in  sl := not RST_POLARITY_G;
       -- Write Ports (wr_clk domain)
       wr_clk : in  sl;
       wr_en  : in  sl := '1';
@@ -58,15 +59,16 @@ begin
 
       FifoAsync_1 : entity surf.FifoAsync
          generic map (
-            TPD_G         => TPD_G,
-            RST_ASYNC_G   => RST_ASYNC_G,
-            MEMORY_TYPE_G => MEMORY_TYPE_G,
-            FWFT_EN_G     => true,
-            SYNC_STAGES_G => SYNC_STAGES_G,
-            PIPE_STAGES_G => PIPE_STAGES_G,
-            DATA_WIDTH_G  => DATA_WIDTH_G,
-            ADDR_WIDTH_G  => ADDR_WIDTH_G,
-            INIT_G        => INIT_C)
+            TPD_G          => TPD_G,
+            RST_POLARITY_G => RST_POLARITY_G,
+            RST_ASYNC_G    => RST_ASYNC_G,
+            MEMORY_TYPE_G  => MEMORY_TYPE_G,
+            FWFT_EN_G      => true,
+            SYNC_STAGES_G  => SYNC_STAGES_G,
+            PIPE_STAGES_G  => PIPE_STAGES_G,
+            DATA_WIDTH_G   => DATA_WIDTH_G,
+            ADDR_WIDTH_G   => ADDR_WIDTH_G,
+            INIT_G         => INIT_C)
          port map (
             rst           => rst,
             wr_clk        => wr_clk,