Release Candidate v2.51.0 #1196
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mapping CLKOUT1 to userClk, which is a useful optional clock reference
adding userCLk to SelectioDeserUltraScale.vhd
### Description - Using "std_logic" instead of "sl" for generics due to issues with SystemVerilog handling VHDL subtype on generics properly
Update RstSync.vhd
adding Pgp4RxLiteLowSpeed.vhd
…REERUN_G=false mode
Updates to AxiLiteSaciMaster.vhd & SaciMaster2.vhd
Mask off the Valid until the gearbox is locked
Pgp4RxLiteLowSpeedLane.vhd Update
Increased range of SACI_NUM_CHIPS_G to support more than 4 chips
…epare for asic deployment
introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to prepare for asic deployment
_Qsfp.py Update
cbakalis-slac
requested changes
Oct 2, 2024
cbakalis-slac
approved these changes
Oct 2, 2024
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Description