Merge pull request #1098 from slaclab/ESCORE-814

Adding more cocoTB modules

axi/axi-lite/rtl/AxiDualPortRam.vhd

@@ -361,11 +361,11 @@ begin
                if (AXI_WR_EN_G) then
                   v.axiAddr        := axiWriteMaster.awaddr(AXI_RAM_ADDR_HIGH_C downto AXI_RAM_ADDR_LOW_C);
                   if (DATA_WIDTH_G <= 32) then
-                     decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_RAM_ADDR_LOW_C-1 downto 0));
+                     v.axiWrStrobe := axiWriteMaster.wstrb;
                   else
                      decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_DEC_ADDR_RANGE_C));
+                     v.axiWrStrobe((decAddrInt+1)*4-1 downto decAddrInt*4) := axiWriteMaster.wstrb;
                   end if;
-                  v.axiWrStrobe((decAddrInt+1)*4-1 downto decAddrInt*4) := axiWriteMaster.wstrb;
                end if;
                axiSlaveWriteResponse(v.axiWriteSlave, ite(AXI_WR_EN_G, AXI_RESP_OK_C, AXI_RESP_SLVERR_C));
             -- Check for read transaction

axi/axi-lite/tb/AxiLiteCrossbarTb.vhd

@@ -0,0 +1,189 @@
+-------------------------------------------------------------------------------
+-- Company    : SLAC National Accelerator Laboratory
+-------------------------------------------------------------------------------
+-- Description: surf.AxiLiteCrossbar cocoTB testbed
+-------------------------------------------------------------------------------
+-- This file is part of 'SLAC Firmware Standard Library'.
+-- It is subject to the license terms in the LICENSE.txt file found in the
+-- top-level directory of this distribution and at:
+--    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of 'SLAC Firmware Standard Library', including this file,
+-- may be copied, modified, propagated, or distributed except according to
+-- the terms contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiLitePkg.all;
+
+entity AxiLiteCrossbarTb is
+   port (
+      -- AXI-Lite Interface
+      S_AXI_ACLK    : in  std_logic;
+      S_AXI_ARESETN : in  std_logic;
+      S_AXI_AWADDR  : in  std_logic_vector(31 downto 0);
+      S_AXI_AWPROT  : in  std_logic_vector(2 downto 0);
+      S_AXI_AWVALID : in  std_logic;
+      S_AXI_AWREADY : out std_logic;
+      S_AXI_WDATA   : in  std_logic_vector(31 downto 0);
+      S_AXI_WSTRB   : in  std_logic_vector(3 downto 0);
+      S_AXI_WVALID  : in  std_logic;
+      S_AXI_WREADY  : out std_logic;
+      S_AXI_BRESP   : out std_logic_vector(1 downto 0);
+      S_AXI_BVALID  : out std_logic;
+      S_AXI_BREADY  : in  std_logic;
+      S_AXI_ARADDR  : in  std_logic_vector(31 downto 0);
+      S_AXI_ARPROT  : in  std_logic_vector(2 downto 0);
+      S_AXI_ARVALID : in  std_logic;
+      S_AXI_ARREADY : out std_logic;
+      S_AXI_RDATA   : out std_logic_vector(31 downto 0);
+      S_AXI_RRESP   : out std_logic_vector(1 downto 0);
+      S_AXI_RVALID  : out std_logic;
+      S_AXI_RREADY  : in  std_logic);
+end AxiLiteCrossbarTb;
+
+architecture mapping of AxiLiteCrossbarTb is
+
+   constant NUM_AXIL_MASTERS_C : positive := 2;
+
+   constant AXIL_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXIL_MASTERS_C-1 downto 0) := genAxiLiteConfig(NUM_AXIL_MASTERS_C, x"0000_0000", 22, 20);
+
+   constant NUM_CASCADE_MASTERS_C : positive := 2;
+
+   constant CASCADE_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_CASCADE_MASTERS_C-1 downto 0) := (
+      0               => (
+         baseAddr     => x"0010_2000",
+         addrBits     => 12,
+         connectivity => X"0001"),
+      1               => (
+         baseAddr     => x"0016_0000",
+         addrBits     => 17,
+         connectivity => X"0001"));
+
+   signal axilClk : sl;
+   signal axilRst : sl;
+
+   signal axilReadMaster  : AxiLiteReadMasterType;
+   signal axilReadSlave   : AxiLiteReadSlaveType;
+   signal axilWriteMaster : AxiLiteWriteMasterType;
+   signal axilWriteSlave  : AxiLiteWriteSlaveType;
+
+   signal axilReadMasters  : AxiLiteReadMasterArray(NUM_AXIL_MASTERS_C-1 downto 0);
+   signal axilReadSlaves   : AxiLiteReadSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0)  := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C);
+   signal axilWriteMasters : AxiLiteWriteMasterArray(NUM_AXIL_MASTERS_C-1 downto 0);
+   signal axilWriteSlaves  : AxiLiteWriteSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C);
+
+   signal cascadeReadMasters  : AxiLiteReadMasterArray(NUM_CASCADE_MASTERS_C-1 downto 0);
+   signal cascadeReadSlaves   : AxiLiteReadSlaveArray(NUM_CASCADE_MASTERS_C-1 downto 0)  := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C);
+   signal cascadeWriteMasters : AxiLiteWriteMasterArray(NUM_CASCADE_MASTERS_C-1 downto 0);
+   signal cascadeWriteSlaves  : AxiLiteWriteSlaveArray(NUM_CASCADE_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C);
+
+begin
+
+   U_ShimLayer : entity surf.SlaveAxiLiteIpIntegrator
+      generic map (
+         EN_ERROR_RESP => true,
+         FREQ_HZ       => 125000000,
+         ADDR_WIDTH    => 32)
+      port map (
+         -- IP Integrator AXI-Lite Interface
+         S_AXI_ACLK      => S_AXI_ACLK,
+         S_AXI_ARESETN   => S_AXI_ARESETN,
+         S_AXI_AWADDR    => S_AXI_AWADDR,
+         S_AXI_AWPROT    => S_AXI_AWPROT,
+         S_AXI_AWVALID   => S_AXI_AWVALID,
+         S_AXI_AWREADY   => S_AXI_AWREADY,
+         S_AXI_WDATA     => S_AXI_WDATA,
+         S_AXI_WSTRB     => S_AXI_WSTRB,
+         S_AXI_WVALID    => S_AXI_WVALID,
+         S_AXI_WREADY    => S_AXI_WREADY,
+         S_AXI_BRESP     => S_AXI_BRESP,
+         S_AXI_BVALID    => S_AXI_BVALID,
+         S_AXI_BREADY    => S_AXI_BREADY,
+         S_AXI_ARADDR    => S_AXI_ARADDR,
+         S_AXI_ARPROT    => S_AXI_ARPROT,
+         S_AXI_ARVALID   => S_AXI_ARVALID,
+         S_AXI_ARREADY   => S_AXI_ARREADY,
+         S_AXI_RDATA     => S_AXI_RDATA,
+         S_AXI_RRESP     => S_AXI_RRESP,
+         S_AXI_RVALID    => S_AXI_RVALID,
+         S_AXI_RREADY    => S_AXI_RREADY,
+         -- SURF AXI-Lite Interface
+         axilClk         => axilClk,
+         axilRst         => axilRst,
+         axilReadMaster  => axilReadMaster,
+         axilReadSlave   => axilReadSlave,
+         axilWriteMaster => axilWriteMaster,
+         axilWriteSlave  => axilWriteSlave);
+
+   U_AXIL_XBAR : entity surf.AxiLiteCrossbar
+      generic map (
+         NUM_SLAVE_SLOTS_G  => 1,
+         NUM_MASTER_SLOTS_G => NUM_AXIL_MASTERS_C,
+         MASTERS_CONFIG_G   => AXIL_XBAR_CONFIG_C)
+      port map (
+         axiClk              => axilClk,
+         axiClkRst           => axilRst,
+         sAxiWriteMasters(0) => axilWriteMaster,
+         sAxiWriteSlaves(0)  => axilWriteSlave,
+         sAxiReadMasters(0)  => axilReadMaster,
+         sAxiReadSlaves(0)   => axilReadSlave,
+         mAxiWriteMasters    => axilWriteMasters,
+         mAxiWriteSlaves     => axilWriteSlaves,
+         mAxiReadMasters     => axilReadMasters,
+         mAxiReadSlaves      => axilReadSlaves);
+
+   U_MEM : entity surf.AxiDualPortRam
+      generic map (
+         ADDR_WIDTH_G => 10,
+         DATA_WIDTH_G => 32)
+      port map (
+         -- Axi Port
+         axiClk         => axilClk,
+         axiRst         => axilRst,
+         axiReadMaster  => axilReadMasters(0),
+         axiReadSlave   => axilReadSlaves(0),
+         axiWriteMaster => axilWriteMasters(0),
+         axiWriteSlave  => axilWriteSlaves(0));
+
+   U_CASCADE_XBAR : entity surf.AxiLiteCrossbar
+      generic map (
+         NUM_SLAVE_SLOTS_G  => 1,
+         NUM_MASTER_SLOTS_G => NUM_CASCADE_MASTERS_C,
+         MASTERS_CONFIG_G   => CASCADE_XBAR_CONFIG_C)
+      port map (
+         axiClk              => axilClk,
+         axiClkRst           => axilRst,
+         sAxiWriteMasters(0) => axilWriteMasters(1),
+         sAxiWriteSlaves(0)  => axilWriteSlaves(1),
+         sAxiReadMasters(0)  => axilReadMasters(1),
+         sAxiReadSlaves(0)   => axilReadSlaves(1),
+         mAxiWriteMasters    => cascadeWriteMasters,
+         mAxiWriteSlaves     => cascadeWriteSlaves,
+         mAxiReadMasters     => cascadeReadMasters,
+         mAxiReadSlaves      => cascadeReadSlaves);
+
+   GEN_VEC :
+   for i in NUM_CASCADE_MASTERS_C-1 downto 0 generate
+
+      U_MEM : entity surf.AxiDualPortRam
+         generic map (
+            ADDR_WIDTH_G => 10,
+            DATA_WIDTH_G => 32)
+         port map (
+            -- Axi Port
+            axiClk         => axilClk,
+            axiRst         => axilRst,
+            axiReadMaster  => cascadeReadMasters(i),
+            axiReadSlave   => cascadeReadSlaves(i),
+            axiWriteMaster => cascadeWriteMasters(i),
+            axiWriteSlave  => cascadeWriteSlaves(i));
+
+   end generate GEN_VEC;
+
+end mapping;

axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd

@@ -0,0 +1,175 @@
+-------------------------------------------------------------------------------
+-- Company    : SLAC National Accelerator Laboratory
+-------------------------------------------------------------------------------
+-- Description: surf.AxiStreamDemux/surf.AxiStreamMux cocoTB testbed
+-------------------------------------------------------------------------------
+-- This file is part of 'SLAC Firmware Standard Library'.
+-- It is subject to the license terms in the LICENSE.txt file found in the
+-- top-level directory of this distribution and at:
+--    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of 'SLAC Firmware Standard Library', including this file,
+-- may be copied, modified, propagated, or distributed except according to
+-- the terms contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiStreamPkg.all;
+
+entity AxiStreamDemuxMuxTb is
+   generic (
+      -- AXI Stream Configuration
+      TUSER_WIDTH_G        : positive range 1 to 8   := 1;
+      TID_WIDTH_G          : positive range 1 to 8   := 1;
+      TDEST_WIDTH_G        : positive range 1 to 8   := 1;
+      TDATA_NUM_BYTES_G    : positive range 1 to 128 := 1;
+      MUX_STREAMS_G        : positive                := 2;
+      PIPE_STAGES_G        : natural                 := 0;
+      ILEAVE_EN_G          : boolean                 := false;
+      ILEAVE_ON_NOTVALID_G : boolean                 := false;
+      ILEAVE_REARB_G       : natural                 := 0;
+      REARB_DELAY_G        : boolean                 := true;
+      FORCED_REARB_HOLD_G  : boolean                 := false);
+   port (
+      -- Clock and Reset
+      AXIS_ACLK     : in  std_logic                                          := '0';
+      AXIS_ARESETN  : in  std_logic                                          := '0';
+      -- IP Integrator Slave AXI Stream Interface
+      S_AXIS_TVALID : in  std_logic                                          := '0';
+      S_AXIS_TDATA  : in  std_logic_vector((8*TDATA_NUM_BYTES_G)-1 downto 0) := (others => '0');
+      S_AXIS_TSTRB  : in  std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0)     := (others => '0');
+      S_AXIS_TKEEP  : in  std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0)     := (others => '0');
+      S_AXIS_TLAST  : in  std_logic                                          := '0';
+      S_AXIS_TDEST  : in  std_logic_vector(TDEST_WIDTH_G-1 downto 0)         := (others => '0');
+      S_AXIS_TID    : in  std_logic_vector(TID_WIDTH_G-1 downto 0)           := (others => '0');
+      S_AXIS_TUSER  : in  std_logic_vector(TUSER_WIDTH_G-1 downto 0)         := (others => '0');
+      S_AXIS_TREADY : out std_logic;
+      -- IP Integrator Master AXI Stream Interface
+      M_AXIS_TVALID : out std_logic;
+      M_AXIS_TDATA  : out std_logic_vector((8*TDATA_NUM_BYTES_G)-1 downto 0);
+      M_AXIS_TSTRB  : out std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0);
+      M_AXIS_TKEEP  : out std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0);
+      M_AXIS_TLAST  : out std_logic;
+      M_AXIS_TDEST  : out std_logic_vector(TDEST_WIDTH_G-1 downto 0);
+      M_AXIS_TID    : out std_logic_vector(TID_WIDTH_G-1 downto 0);
+      M_AXIS_TUSER  : out std_logic_vector(TUSER_WIDTH_G-1 downto 0);
+      M_AXIS_TREADY : in  std_logic);
+end AxiStreamDemuxMuxTb;
+
+architecture mapping of AxiStreamDemuxMuxTb is
+
+   signal axisClk : sl := '0';
+   signal axisRst : sl := '0';
+
+   signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
+   signal sAxisSlave  : AxiStreamSlaveType  := AXI_STREAM_SLAVE_FORCE_C;
+
+   signal axisMasters : AxiStreamMasterArray(MUX_STREAMS_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C);
+   signal axisSlaves  : AxiStreamSlaveArray(MUX_STREAMS_G-1 downto 0)  := (others => AXI_STREAM_SLAVE_FORCE_C);
+
+   signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
+   signal mAxisSlave  : AxiStreamSlaveType  := AXI_STREAM_SLAVE_FORCE_C;
+
+begin
+
+   U_ShimLayerSlave : entity surf.SlaveAxiStreamIpIntegrator
+      generic map (
+         INTERFACENAME   => "S_AXIS",
+         HAS_TLAST       => 1,
+         HAS_TKEEP       => 1,
+         HAS_TSTRB       => 1,
+         HAS_TREADY      => 1,
+         TUSER_WIDTH     => TUSER_WIDTH_G,
+         TID_WIDTH       => TID_WIDTH_G,
+         TDEST_WIDTH     => TDEST_WIDTH_G,
+         TDATA_NUM_BYTES => TDATA_NUM_BYTES_G)
+      port map (
+         -- IP Integrator AXI Stream Interface
+         S_AXIS_ACLK    => AXIS_ACLK,
+         S_AXIS_ARESETN => AXIS_ARESETN,
+         S_AXIS_TVALID  => S_AXIS_TVALID,
+         S_AXIS_TDATA   => S_AXIS_TDATA,
+         S_AXIS_TSTRB   => S_AXIS_TSTRB,
+         S_AXIS_TKEEP   => S_AXIS_TKEEP,
+         S_AXIS_TLAST   => S_AXIS_TLAST,
+         S_AXIS_TDEST   => S_AXIS_TDEST,
+         S_AXIS_TID     => S_AXIS_TID,
+         S_AXIS_TUSER   => S_AXIS_TUSER,
+         S_AXIS_TREADY  => S_AXIS_TREADY,
+         -- SURF AXI Stream Interface
+         axisClk        => axisClk,
+         axisRst        => axisRst,
+         axisMaster     => sAxisMaster,
+         axisSlave      => sAxisSlave);
+
+   U_DeMux : entity surf.AxiStreamDeMux
+      generic map (
+         NUM_MASTERS_G => MUX_STREAMS_G,
+         PIPE_STAGES_G => PIPE_STAGES_G)
+      port map (
+         -- Clock and reset
+         axisClk      => axisClk,
+         axisRst      => axisRst,
+         -- Slave
+         sAxisMaster  => sAxisMaster,
+         sAxisSlave   => sAxisSlave,
+         -- Masters
+         mAxisMasters => axisMasters,
+         mAxisSlaves  => axisSlaves);
+
+   U_Mux : entity surf.AxiStreamMux
+      generic map (
+         NUM_SLAVES_G         => MUX_STREAMS_G,
+         PIPE_STAGES_G        => PIPE_STAGES_G,
+         ILEAVE_EN_G          => ILEAVE_EN_G,
+         ILEAVE_ON_NOTVALID_G => ILEAVE_ON_NOTVALID_G,
+         ILEAVE_REARB_G       => ILEAVE_REARB_G,
+         REARB_DELAY_G        => REARB_DELAY_G,
+         FORCED_REARB_HOLD_G  => FORCED_REARB_HOLD_G)
+      port map (
+         -- Clock and reset
+         axisClk      => axisClk,
+         axisRst      => axisRst,
+         -- Slaves
+         sAxisMasters => axisMasters,
+         sAxisSlaves  => axisSlaves,
+         -- Master
+         mAxisMaster  => mAxisMaster,
+         mAxisSlave   => mAxisSlave);
+
+   U_ShimLayerMaster : entity surf.MasterAxiStreamIpIntegrator
+      generic map (
+         INTERFACENAME   => "M_AXIS",
+         HAS_TLAST       => 1,
+         HAS_TKEEP       => 1,
+         HAS_TSTRB       => 1,
+         HAS_TREADY      => 1,
+         TUSER_WIDTH     => TUSER_WIDTH_G,
+         TID_WIDTH       => TID_WIDTH_G,
+         TDEST_WIDTH     => TDEST_WIDTH_G,
+         TDATA_NUM_BYTES => TDATA_NUM_BYTES_G)
+      port map (
+         -- IP Integrator AXI Stream Interface
+         M_AXIS_ACLK    => AXIS_ACLK,
+         M_AXIS_ARESETN => AXIS_ARESETN,
+         M_AXIS_TVALID  => M_AXIS_TVALID,
+         M_AXIS_TDATA   => M_AXIS_TDATA,
+         M_AXIS_TSTRB   => M_AXIS_TSTRB,
+         M_AXIS_TKEEP   => M_AXIS_TKEEP,
+         M_AXIS_TLAST   => M_AXIS_TLAST,
+         M_AXIS_TDEST   => M_AXIS_TDEST,
+         M_AXIS_TID     => M_AXIS_TID,
+         M_AXIS_TUSER   => M_AXIS_TUSER,
+         M_AXIS_TREADY  => M_AXIS_TREADY,
+         -- SURF AXI Stream Interface
+         axisClk        => open,
+         axisRst        => open,
+         axisMaster     => mAxisMaster,
+         axisSlave      => mAxisSlave);
+
+end mapping;