merge master into RL (#94)

* Update RL (#56)

* fix:remove hashvalue when popping graphs in push_back; refactor shrink

* fix: wrong error raising in graph buffer

* fix: do not shrink buffer according to sys mem usage

* fix: do not pop the graph to push

* fix: do not pop the graph to push

* feat: change mem control policy

* feat: change mem control policy

* Added two Rigetti ecc sets for experiment

* refactor: add some scripts

* fix scripts

* Added rigetti rotation merging circuits

* feat: add configs and scripts for rigetti set

* feat: add scripts for cx on t_tdg

* fix: gate set for t_tdg

* Added two gate types in cython

* fix: gate set for rigetti set

* feat: add scripts for tdg_rm

* fix:d script for tdg_rm

* fix:change name for tdg_rm

* fix: configs for tuning tdg

* feat: add scripts for darawing full seq

* feat: add scripts for darawing full seq

* fix: scripts

* Added rigetti 3, 6 ecc set

* fix: nam scripts and actor.py

* Added some rigetti circuits, a qasm converter, and modified the graph.from_qasm api

* Remove debug outputs

* minor changes

* feat: add test_rigetti

* fix: test_rigetti

* feat: add test tdg rm cx

* Fixed bug in graph::from_qasm

* Fixed some circuits

* Delete some rigetti benchmarks

* Added a rigetti 3, 3, 5 ecc set

* feat: run new rigetti circs

* update ipynb, including vis_seq

* fix: wrong circ dir in test_t_tdg_rm_cx.py

* Modified tasograph.cpp

* Added 4 gates ry1, ry3, rxx1, rxx3

* Add a ionq ecc set

* Added ionq circs, normalized

* feat: add BFS scripts for ionq

* feat: add RL config for IonQ

* feat: add RL config for IonQ

* feat: add RL config for IonQ

* Fixed a bug in Graph::from_qasm_file

* fix: increase num_gate_types

* New version of toffoli flip

* Added 6 nam benchmark circuits

* fix: set num_gate_types for Nam and TDG

* add ipynb to parse log

* feat: output best graph to a specified folder; close #54

Co-authored-by: zikun-li <[email protected]>

* Add CP (controlled phase) gate

* Add support of comment line and empty line to Graph::from_qasm_file

* [qasm] Also ignore barrier and measure

* [gate] Add is_sparse for sparse matrices

* [Refactor] Rename "DAG" to "CircuitSeq" (#61)

* [Refactor] Rename "DAG" to "CircuitSeq"

* fix compilation error

* [QASM] Support multiple quantum registers (#63)

* [qasm] Add CircuitSeq::from_qasm_file() (#64)

* [qasm] Add one kind of parameter format support in QASM parser (#65)

* [qasm] Store input parameters in the context

* [qasm] Add support of U gate

* [gate] Add some support functions for controlled gates (#67)

* Add HiGHS solver as a submodule (#70)

* fix: update isort in pre-commit to resolve its issue with newer python

* fix: wrong branch name

* [gate] Add CU1 gate (#75)

* Update Simulation (#77)

* Add MQT benchmarks and code skeleton for test_simulation

* Use Graph::from_qasm_file

* Add support of comment line and empty line to Graph::from_qasm_file

* [qasm] Also ignore barrier and measure

* Use dj benchmark

* Add MQT benchmarks

* [gate] Add is_sparse for sparse matrices

(cherry picked from commit 8a29479)

* Heuristics in SnuQS

* Experiment for 40-42q, 12-33k, 9 circuits

* Experiment for 40-42q, 12-33k, 9 circuits

* [refactor] Rename "DAG" to "CircuitSeq" in test_simulation.cpp

* Add ILP

* ILP for the full benchmark

* Fix example k value

* Fix dependencies

* Add some outputs

* Fix redundant dependencies

* Print out schedules

* Use HiGHS solver

* Add tiebreaker for heuristics and output the number of iterations (number of shuffles plus one)

* Use CircuitSeq::from_qasm_file in test_simulation

* Add 3 more benchmark circuits

* Multiple qregs for ILP

* restore k

* Remove initial default configuration in heuristics in test_simulation

* [qasm] Add support of U gate

* Update experiments for test_simulation.cpp and ilp.py

* [Simulation] Add schedule and a function to compute the number of down sets

* Test computing the number of down sets

* debug

* [Simulation] Dynamic programming to compute the kernel schedule

* [simulation] Add an optimization to the DP

* [simulation] Fix a bug in the DP

* [simulation] Add absorbing qubits to the DP

* Add 29-qubit circuits and fix absorbing qubits to be sets of sets

* Add 29-qubit circuits

* Not record the result kernels when not needed

* Integrate sim (#68)

* [simulator] initial attempt to integrate into qartz

* [simulator] fix compilation error, cmake version at least 3.18

* [simulator] set using simulator to be optional

* [simulator] set using simulator optional

* [simulator] do matrix shuffle to guarantee the matrix is for increasing qubit order

* [simulator] matrix shuffle

* [simulator] virtual/physical qubit mapping when applying gates

* [simulator] fix some bugs, tested on one device

* [simulator] fix some bugs, tested on 2-devices

* pre-commit

* [Simulation] Use pybind11 to integrate ILP into the simulator (#69)

* [Simulation] Use pybind11 to integrate ILP into the simulator

* Add pybind11 in requirements.txt

* Add pybind11 to env.yml

* Fix linker error on Linux

* Make pybind.cpp not dependent on the working directory

* Restore circuit location in test_simulation.cpp

* Fix the environment on Windows

* [simulation] Add the s array to ILP and print the running time in test_simulation (#71)

* [simulation] Fix a bug about ILP and DP (#72)

* [bug] Amend #72

* Fix Windows environment (#74)

* Fix Windows environment

* Code format

* Code format

* Code format

* [gate] Add CU1 gate

* implement a distributed simulator using legion

* Multi-node Simulator (mpi-based) (#76)

* [simulator] init multi-node impl

* [simulator][multi-node] fix some compilation error

* [simulator][multi-node] fix some error

* [simulator][multi-node] tested on 2 p3.2xlarge node

* [simulator][multi-node] added profiling, ILP some error

* [simulator][multi-node] fix some resource handle error

* [simulator][multi-node] for parallelcluster

* [simulator][multi-node] add more circuits

* [simulator][multi-node] do not block creating event

* [simulator][multi-node]fix sume bugs

* add some circuits

* pre-commit

* comment back quartz tests

---------

Co-authored-by: Ubuntu <[email protected]>

---------

Co-authored-by: shiyi.c_98 <[email protected]>
Co-authored-by: Zhihao Jia <[email protected]>
Co-authored-by: Ubuntu <[email protected]>

* Update Simulation (#81)

* Add MQT benchmarks and code skeleton for test_simulation

* Use Graph::from_qasm_file

* Add support of comment line and empty line to Graph::from_qasm_file

* [qasm] Also ignore barrier and measure

* Use dj benchmark

* Add MQT benchmarks

* [gate] Add is_sparse for sparse matrices

(cherry picked from commit 8a29479)

* Heuristics in SnuQS

* Experiment for 40-42q, 12-33k, 9 circuits

* Experiment for 40-42q, 12-33k, 9 circuits

* [refactor] Rename "DAG" to "CircuitSeq" in test_simulation.cpp

* Add ILP

* ILP for the full benchmark

* Fix example k value

* Fix dependencies

* Add some outputs

* Fix redundant dependencies

* Print out schedules

* Use HiGHS solver

* Add tiebreaker for heuristics and output the number of iterations (number of shuffles plus one)

* Use CircuitSeq::from_qasm_file in test_simulation

* Add 3 more benchmark circuits

* Multiple qregs for ILP

* restore k

* Remove initial default configuration in heuristics in test_simulation

* [qasm] Add support of U gate

* Update experiments for test_simulation.cpp and ilp.py

* [Simulation] Add schedule and a function to compute the number of down sets

* Test computing the number of down sets

* debug

* [Simulation] Dynamic programming to compute the kernel schedule

* [simulation] Add an optimization to the DP

* [simulation] Fix a bug in the DP

* [simulation] Add absorbing qubits to the DP

* Add 29-qubit circuits and fix absorbing qubits to be sets of sets

* Add 29-qubit circuits

* Not record the result kernels when not needed

* Integrate sim (#68)

* [simulator] initial attempt to integrate into qartz

* [simulator] fix compilation error, cmake version at least 3.18

* [simulator] set using simulator to be optional

* [simulator] set using simulator optional

* [simulator] do matrix shuffle to guarantee the matrix is for increasing qubit order

* [simulator] matrix shuffle

* [simulator] virtual/physical qubit mapping when applying gates

* [simulator] fix some bugs, tested on one device

* [simulator] fix some bugs, tested on 2-devices

* pre-commit

* [Simulation] Use pybind11 to integrate ILP into the simulator (#69)

* [Simulation] Use pybind11 to integrate ILP into the simulator

* Add pybind11 in requirements.txt

* Add pybind11 to env.yml

* Fix linker error on Linux

* Make pybind.cpp not dependent on the working directory

* Restore circuit location in test_simulation.cpp

* Fix the environment on Windows

* [simulation] Add the s array to ILP and print the running time in test_simulation (#71)

* [simulation] Fix a bug about ILP and DP (#72)

* [bug] Amend #72

* Fix Windows environment (#74)

* Fix Windows environment

* Code format

* Code format

* Code format

* [gate] Add CU1 gate

* implement a distributed simulator using legion

* Multi-node Simulator (mpi-based) (#76)

* [simulator] init multi-node impl

* [simulator][multi-node] fix some compilation error

* [simulator][multi-node] fix some error

* [simulator][multi-node] tested on 2 p3.2xlarge node

* [simulator][multi-node] added profiling, ILP some error

* [simulator][multi-node] fix some resource handle error

* [simulator][multi-node] for parallelcluster

* [simulator][multi-node] add more circuits

* [simulator][multi-node] do not block creating event

* [simulator][multi-node]fix sume bugs

* add some circuits

* pre-commit

* comment back quartz tests

---------

Co-authored-by: Ubuntu <[email protected]>

* [Simulation] Add an option to not consider single-qubit gates in DP (#78)

* [Simulation] DP for shared-memory gates (#80)

* Add Kernel and KernelCost classes

* Schedule::compute_end_schedule() now considers shared-memory kernels

* Include kernel type in Kernel::to_string()

* Fix missing single-qubit gates

* DP for shared-memory kernels

* Remove TODO about controlled gates

* Code format

---------

Co-authored-by: shiyi.c_98 <[email protected]>
Co-authored-by: Zhihao Jia <[email protected]>
Co-authored-by: Ubuntu <[email protected]>

* [simulation] Fix CX in execution schedules when the target is global (#82)

* [simulation] Fix CX being put into execution schedule when the target is global

* refine criteria

* edit comment

* [bug] Fix clone_from() copying hash value incorrectly (#84)

* [simulation] Restrict the Swap gate as local-only (#85)

* [simulation] Consider cacheline qubits in DP for shared-memory kernels (#83)

* Change the type of Schedule::local_qubit_ from vector<bool> to vector<int>

* [simulation] Consider cacheline qubits in DP for shared-memory kernels

* Apply the new algorithm and fix compilation error in debug mode

* Record global qubits

* Ecc pruning dev (#86)

* Add a pass to eliminate ecc classes that are equivalent under qubit permutation

* Add a pass to eliminate ecc classes that are equivalent under qubit permutation

* Modified kNumOptimizationsToPerform

* fix u3 matrix implementation (#87)

* Fix bug

* Eliminate u3 gate if parameters are all 0

* fix: conflicts

* [simulation] Fix non-executable global gates in kernels (#91)

* Fixed compilation error caused by the obsolete name 'DAG'

* Fix bug caused by obsolete name 'DAG'

---------

Co-authored-by: zikun-li <[email protected]>
Co-authored-by: xumingkuan <[email protected]>
Co-authored-by: shiyi.c_98 <[email protected]>
Co-authored-by: Zhihao Jia <[email protected]>
Co-authored-by: Ubuntu <[email protected]>
Co-authored-by: zikun-li <[email protected]>
Co-authored-by: Shaohan Hu <[email protected]>

experiment/ionq_circs/dj_nativegates_ionq_qiskit_opt0_10_norm.qasm

@@ -0,0 +1,98 @@
+OPENQASM 2.0;
+include "qelib1.inc";
+qreg q[10];
+creg c[9];
+ry1 q[0];
+x q[0];
+x q[0];
+ry1 q[0];
+ry1 q[1];
+x q[1];
+x q[1];
+ry1 q[1];
+ry1 q[2];
+x q[2];
+x q[2];
+ry1 q[2];
+ry1 q[3];
+x q[3];
+ry1 q[3];
+ry1 q[4];
+x q[4];
+ry1 q[4];
+ry1 q[5];
+x q[5];
+ry1 q[5];
+ry1 q[6];
+x q[6];
+x q[6];
+ry1 q[6];
+ry1 q[7];
+x q[7];
+x q[7];
+ry1 q[7];
+ry1 q[8];
+x q[8];
+ry1 q[8];
+x q[9];
+ry1 q[9];
+x q[9];
+rxx1 q[0],q[9];
+rx3 q[0];
+ry3 q[0];
+x q[0];
+ry1 q[0];
+x q[0];
+rx3 q[9];
+rxx1 q[1],q[9];
+rx3 q[1];
+ry3 q[1];
+x q[1];
+ry1 q[1];
+x q[1];
+rx3 q[9];
+rxx1 q[2],q[9];
+rx3 q[2];
+ry3 q[2];
+x q[2];
+ry1 q[2];
+x q[2];
+rx3 q[9];
+rxx1 q[3],q[9];
+rx3 q[3];
+ry3 q[3];
+ry1 q[3];
+x q[3];
+rx3 q[9];
+rxx1 q[4],q[9];
+rx3 q[4];
+ry3 q[4];
+ry1 q[4];
+x q[4];
+rx3 q[9];
+rxx1 q[5],q[9];
+rx3 q[5];
+ry3 q[5];
+ry1 q[5];
+x q[5];
+rx3 q[9];
+rxx1 q[6],q[9];
+rx3 q[6];
+ry3 q[6];
+x q[6];
+ry1 q[6];
+x q[6];
+rx3 q[9];
+rxx1 q[7],q[9];
+rx3 q[7];
+ry3 q[7];
+x q[7];
+ry1 q[7];
+x q[7];
+rx3 q[9];
+rxx1 q[8],q[9];
+rx3 q[8];
+ry3 q[8];
+ry1 q[8];
+x q[8];
+rx3 q[9];

experiment/ionq_circs/ghz_nativegates_ionq_qiskit_opt0_10_norm.qasm

@@ -0,0 +1,51 @@
+OPENQASM 2.0;
+include "qelib1.inc";
+qreg q[10];
+creg meas[10];
+ry1 q[9];
+x q[9];
+ry1 q[9];
+rxx1 q[9],q[8];
+rx3 q[8];
+ry1 q[8];
+rxx1 q[8],q[7];
+rx3 q[7];
+ry1 q[7];
+rxx1 q[7],q[6];
+rx3 q[6];
+ry1 q[6];
+rxx1 q[6],q[5];
+rx3 q[5];
+ry1 q[5];
+rxx1 q[5],q[4];
+rx3 q[4];
+ry1 q[4];
+rxx1 q[4],q[3];
+rx3 q[3];
+ry1 q[3];
+rxx1 q[3],q[2];
+rx3 q[2];
+ry1 q[2];
+rxx1 q[2],q[1];
+rx3 q[1];
+ry1 q[1];
+rxx1 q[1],q[0];
+rx3 q[0];
+rx3 q[1];
+ry3 q[1];
+rx3 q[2];
+ry3 q[2];
+rx3 q[3];
+ry3 q[3];
+rx3 q[4];
+ry3 q[4];
+rx3 q[5];
+ry3 q[5];
+rx3 q[6];
+ry3 q[6];
+rx3 q[7];
+ry3 q[7];
+rx3 q[8];
+ry3 q[8];
+rx3 q[9];
+ry3 q[9];

experiment/ionq_circs/graphstate_nativegates_ionq_qiskit_opt0_10_norm.qasm

@@ -0,0 +1,114 @@
+OPENQASM 2.0;
+include "qelib1.inc";
+qreg q[10];
+creg meas[10];
+ry1 q[0];
+x q[0];
+ry1 q[0];
+ry1 q[1];
+x q[1];
+ry1 q[1];
+x q[1];
+rxx1 q[0],q[1];
+rx3 q[0];
+ry3 q[0];
+ry1 q[0];
+rx3 q[1];
+ry1 q[1];
+x q[1];
+ry1 q[1];
+ry1 q[2];
+x q[2];
+ry1 q[2];
+ry1 q[3];
+x q[3];
+ry1 q[3];
+x q[3];
+rxx1 q[2],q[3];
+rx3 q[2];
+ry3 q[2];
+ry1 q[2];
+rx3 q[3];
+ry1 q[3];
+x q[3];
+ry1 q[3];
+ry1 q[4];
+x q[4];
+ry1 q[4];
+x q[4];
+rxx1 q[3],q[4];
+rx3 q[3];
+ry3 q[3];
+rx3 q[4];
+ry1 q[4];
+x q[4];
+ry1 q[4];
+ry1 q[5];
+x q[5];
+ry1 q[5];
+x q[5];
+rxx1 q[0],q[5];
+rx3 q[0];
+ry3 q[0];
+rx3 q[5];
+ry1 q[5];
+x q[5];
+ry1 q[5];
+x q[5];
+rxx1 q[4],q[5];
+rx3 q[4];
+ry3 q[4];
+rx3 q[5];
+ry1 q[5];
+x q[5];
+ry1 q[6];
+x q[6];
+ry1 q[6];
+x q[6];
+rxx1 q[1],q[6];
+rx3 q[1];
+ry3 q[1];
+rx3 q[6];
+ry1 q[6];
+x q[6];
+ry1 q[6];
+x q[6];
+rxx1 q[2],q[6];
+rx3 q[2];
+ry3 q[2];
+rx3 q[6];
+ry1 q[6];
+x q[6];
+ry1 q[7];
+x q[7];
+ry1 q[7];
+ry1 q[8];
+x q[8];
+ry1 q[8];
+x q[8];
+rxx1 q[7],q[8];
+rx3 q[7];
+ry3 q[7];
+ry1 q[7];
+rx3 q[8];
+ry1 q[8];
+x q[8];
+ry1 q[8];
+ry1 q[9];
+x q[9];
+ry1 q[9];
+x q[9];
+rxx1 q[7],q[9];
+rx3 q[7];
+ry3 q[7];
+rx3 q[9];
+ry1 q[9];
+x q[9];
+ry1 q[9];
+x q[9];
+rxx1 q[8],q[9];
+rx3 q[8];
+ry3 q[8];
+rx3 q[9];
+ry1 q[9];
+x q[9];