cpu: aarch64: Expand ARM SVE support in jit_uni_batch_normalization

Added sve_256 in the implementation list
Update jit_uni_batch_normalization.cpp
Updated the block size definition to accommodate different ISAs.
Added 'OR' conditions to extend support for additonal block_size.
Predicate registers are set according to isa vector length.
ldr and str instruction changed to ldw1 and stw1 respectively. To support load and store operations as per ISA.