cpu: aarch64: batch_normalization : Expand ARM SVE support in jit_uni_batch_normalization #1918
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Description
This commit enhances the existing ARM SVE support in jit_uni_batch_normalization to include additional vector length compatibility. The changes made are for implementation of different ARM SVE vector length.
Major Code changes:
Updated the block size definition to accommodate other SVE vector length.
Added 'OR' and 'AND' conditions to extend support for other SVE vector.
Predicate registers are set according to isa vector length.
ldr and str instructions are replaced by ld1w and st1w respectively. For appropriate load and strore operation considering isa vector length.
Checklist
General
[✓] Do all unit and benchdnn tests (make test and make test_benchdnn_*) pass locally for each commit? Yes
Test output is same with and without this commit.
make test output:
99% tests passed, 1 tests failed out of 103
Total Test time (real) = 36.37 sec
The following tests FAILED:
102 - test_graph_unit_cpu (Failed)
Errors while running CTest
Output from these tests are in: /home/nikhil/TEST/oneDNN/build/Testing/Temporary/LastTest.log
Use "--rerun-failed --output-on-failure" to re-run the failed cases verbosely.
make: *** [Makefile:71: test] Error 8
make test_benchdnn_* output:
make: *** No rule to make target 'test_benchdnn_*'. Stop.
make test_benchdnn_bnorm_ci_cpu/fast output.
tests:4445 passed:1232 skipped:2989 mistrusted:224 unimplemented:0 invalid_arguments:0 failed:0 listed:0