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Regen with chiptool d29063045446448526e3e0c19857f10e32992386
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@Dirbaio
Dirbaio committed Jun 29, 2023
1 parent 60a3714 commit 0821b19
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Showing 31 changed files with 3,090 additions and 758 deletions.
2 changes: 1 addition & 1 deletion src/adc/regs.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -293,7 +293,7 @@ impl Default for Fifo {
Fifo(0)
}
}
#[doc = "Interrupt Force"]
#[doc = "Interrupt Enable"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Int(pub u32);
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16 changes: 8 additions & 8 deletions src/busctrl/regs.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -77,18 +77,18 @@ impl Default for BusPriorityAck {
BusPriorityAck(0)
}
}
#[doc = "Bus fabric performance counter 2"]
#[doc = "Bus fabric performance counter 0"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Perfctr(pub u32);
impl Perfctr {
#[doc = "Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"]
#[doc = "Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"]
#[inline(always)]
pub const fn perfctr(&self) -> u32 {
let val = (self.0 >> 0usize) & 0x00ff_ffff;
val as u32
}
#[doc = "Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"]
#[doc = "Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"]
#[inline(always)]
pub fn set_perfctr(&mut self, val: u32) {
self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
Expand All @@ -100,21 +100,21 @@ impl Default for Perfctr {
Perfctr(0)
}
}
#[doc = "Bus fabric performance event select for PERFCTR0"]
#[doc = "Bus fabric performance event select for PERFCTR1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Perfsel(pub u32);
impl Perfsel {
#[doc = "Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
#[doc = "Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
#[inline(always)]
pub const fn perfsel(&self) -> super::vals::Perfsel {
let val = (self.0 >> 0usize) & 0x1f;
super::vals::Perfsel(val as u8)
super::vals::Perfsel::from_bits(val as u8)
}
#[doc = "Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
#[doc = "Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
#[inline(always)]
pub fn set_perfsel(&mut self, val: super::vals::Perfsel) {
self.0 = (self.0 & !(0x1f << 0usize)) | (((val.0 as u32) & 0x1f) << 0usize);
self.0 = (self.0 & !(0x1f << 0usize)) | (((val.to_bits() as u32) & 0x1f) << 0usize);
}
}
impl Default for Perfsel {
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77 changes: 55 additions & 22 deletions src/busctrl/vals.rs
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Original file line number Diff line number Diff line change
@@ -1,25 +1,58 @@
#[repr(transparent)]
#[repr(u8)]
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
pub struct Perfsel(pub u8);
pub enum Perfsel {
APB_CONTESTED = 0,
APB = 0x01,
FASTPERI_CONTESTED = 0x02,
FASTPERI = 0x03,
SRAM5_CONTESTED = 0x04,
SRAM5 = 0x05,
SRAM4_CONTESTED = 0x06,
SRAM4 = 0x07,
SRAM3_CONTESTED = 0x08,
SRAM3 = 0x09,
SRAM2_CONTESTED = 0x0a,
SRAM2 = 0x0b,
SRAM1_CONTESTED = 0x0c,
SRAM1 = 0x0d,
SRAM0_CONTESTED = 0x0e,
SRAM0 = 0x0f,
XIP_MAIN_CONTESTED = 0x10,
XIP_MAIN = 0x11,
ROM_CONTESTED = 0x12,
ROM = 0x13,
_RESERVED_14 = 0x14,
_RESERVED_15 = 0x15,
_RESERVED_16 = 0x16,
_RESERVED_17 = 0x17,
_RESERVED_18 = 0x18,
_RESERVED_19 = 0x19,
_RESERVED_1a = 0x1a,
_RESERVED_1b = 0x1b,
_RESERVED_1c = 0x1c,
_RESERVED_1d = 0x1d,
_RESERVED_1e = 0x1e,
_RESERVED_1f = 0x1f,
}
impl Perfsel {
pub const APB_CONTESTED: Self = Self(0);
pub const APB: Self = Self(0x01);
pub const FASTPERI_CONTESTED: Self = Self(0x02);
pub const FASTPERI: Self = Self(0x03);
pub const SRAM5_CONTESTED: Self = Self(0x04);
pub const SRAM5: Self = Self(0x05);
pub const SRAM4_CONTESTED: Self = Self(0x06);
pub const SRAM4: Self = Self(0x07);
pub const SRAM3_CONTESTED: Self = Self(0x08);
pub const SRAM3: Self = Self(0x09);
pub const SRAM2_CONTESTED: Self = Self(0x0a);
pub const SRAM2: Self = Self(0x0b);
pub const SRAM1_CONTESTED: Self = Self(0x0c);
pub const SRAM1: Self = Self(0x0d);
pub const SRAM0_CONTESTED: Self = Self(0x0e);
pub const SRAM0: Self = Self(0x0f);
pub const XIP_MAIN_CONTESTED: Self = Self(0x10);
pub const XIP_MAIN: Self = Self(0x11);
pub const ROM_CONTESTED: Self = Self(0x12);
pub const ROM: Self = Self(0x13);
#[inline(always)]
pub const fn from_bits(val: u8) -> Perfsel {
unsafe { core::mem::transmute(val & 0x1f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Perfsel {
#[inline(always)]
fn from(val: u8) -> Perfsel {
Perfsel::from_bits(val)
}
}
impl From<Perfsel> for u8 {
#[inline(always)]
fn from(val: Perfsel) -> u8 {
Perfsel::to_bits(val)
}
}
42 changes: 21 additions & 21 deletions src/clocks/regs.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -7,12 +7,12 @@ impl ClkAdcCtrl {
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkAdcCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x07;
super::vals::ClkAdcCtrlAuxsrc(val as u8)
super::vals::ClkAdcCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkAdcCtrlAuxsrc) {
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.0 as u32) & 0x07) << 5usize);
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
Expand Down Expand Up @@ -97,12 +97,12 @@ impl ClkGpoutCtrl {
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkGpoutCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x0f;
super::vals::ClkGpoutCtrlAuxsrc(val as u8)
super::vals::ClkGpoutCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkGpoutCtrlAuxsrc) {
self.0 = (self.0 & !(0x0f << 5usize)) | (((val.0 as u32) & 0x0f) << 5usize);
self.0 = (self.0 & !(0x0f << 5usize)) | (((val.to_bits() as u32) & 0x0f) << 5usize);
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
Expand Down Expand Up @@ -209,12 +209,12 @@ impl ClkPeriCtrl {
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkPeriCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x07;
super::vals::ClkPeriCtrlAuxsrc(val as u8)
super::vals::ClkPeriCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkPeriCtrlAuxsrc) {
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.0 as u32) & 0x07) << 5usize);
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
Expand Down Expand Up @@ -254,23 +254,23 @@ impl ClkRefCtrl {
#[inline(always)]
pub const fn src(&self) -> super::vals::ClkRefCtrlSrc {
let val = (self.0 >> 0usize) & 0x03;
super::vals::ClkRefCtrlSrc(val as u8)
super::vals::ClkRefCtrlSrc::from_bits(val as u8)
}
#[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
#[inline(always)]
pub fn set_src(&mut self, val: super::vals::ClkRefCtrlSrc) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkRefCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x03;
super::vals::ClkRefCtrlAuxsrc(val as u8)
super::vals::ClkRefCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkRefCtrlAuxsrc) {
self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize);
self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize);
}
}
impl Default for ClkRefCtrl {
Expand Down Expand Up @@ -311,12 +311,12 @@ impl ClkRtcCtrl {
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkRtcCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x07;
super::vals::ClkRtcCtrlAuxsrc(val as u8)
super::vals::ClkRtcCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkRtcCtrlAuxsrc) {
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.0 as u32) & 0x07) << 5usize);
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
Expand Down Expand Up @@ -412,23 +412,23 @@ impl ClkSysCtrl {
#[inline(always)]
pub const fn src(&self) -> super::vals::ClkSysCtrlSrc {
let val = (self.0 >> 0usize) & 0x01;
super::vals::ClkSysCtrlSrc(val as u8)
super::vals::ClkSysCtrlSrc::from_bits(val as u8)
}
#[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
#[inline(always)]
pub fn set_src(&mut self, val: super::vals::ClkSysCtrlSrc) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkSysCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x07;
super::vals::ClkSysCtrlAuxsrc(val as u8)
super::vals::ClkSysCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkSysCtrlAuxsrc) {
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.0 as u32) & 0x07) << 5usize);
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
}
}
impl Default for ClkSysCtrl {
Expand Down Expand Up @@ -557,12 +557,12 @@ impl ClkUsbCtrl {
#[inline(always)]
pub const fn auxsrc(&self) -> super::vals::ClkUsbCtrlAuxsrc {
let val = (self.0 >> 5usize) & 0x07;
super::vals::ClkUsbCtrlAuxsrc(val as u8)
super::vals::ClkUsbCtrlAuxsrc::from_bits(val as u8)
}
#[doc = "Selects the auxiliary clock source, will glitch when switching"]
#[inline(always)]
pub fn set_auxsrc(&mut self, val: super::vals::ClkUsbCtrlAuxsrc) {
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.0 as u32) & 0x07) << 5usize);
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
}
#[doc = "Asynchronously kills the clock generator"]
#[inline(always)]
Expand Down Expand Up @@ -1228,11 +1228,11 @@ impl Fc0src {
#[inline(always)]
pub const fn fc0_src(&self) -> super::vals::Fc0src {
let val = (self.0 >> 0usize) & 0xff;
super::vals::Fc0src(val as u8)
super::vals::Fc0src::from_bits(val as u8)
}
#[inline(always)]
pub fn set_fc0_src(&mut self, val: super::vals::Fc0src) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val.0 as u32) & 0xff) << 0usize);
self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize);
}
}
impl Default for Fc0src {
Expand Down Expand Up @@ -1341,7 +1341,7 @@ impl Default for Fc0status {
Fc0status(0)
}
}
#[doc = "Interrupt status after masking & forcing"]
#[doc = "Interrupt Force"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Int(pub u32);
Expand Down
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