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Fix a few wrong transforms.
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Dirbaio committed Jun 29, 2023
1 parent 2ca948c commit 60a3714
Showing 1 changed file with 8 additions and 2 deletions.
10 changes: 8 additions & 2 deletions svd/rp2040.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -21,10 +21,13 @@ transforms:
- MergeFieldsets:
from: dma::regs::Ch\d+CtrlTrig
to: dma::regs::CtrlTrig
- RenameFields:
fieldset: dma::regs::Ch\d+DbgCtdreq
from: ch\d+_(.*)
to: $1
- MergeFieldsets:
from: dma::regs::Ch\d+DbgCtdreq
to: dma::regs::DbgCtdreq
check: Layout
- MakeBlock:
blocks: dma::Dma
from: ch(\d+)_(.*)
Expand Down Expand Up @@ -297,10 +300,13 @@ transforms:
- MergeFieldsets:
from: clocks::regs::Int.
to: clocks::regs::Int
- RenameEnumVariants:
enum: clocks::vals::ClkGpout\dCtrlAuxsrc
from: ROSC_CLKSRC_PH
to: ROSC_CLKSRC
- MergeEnums:
from: clocks::vals::ClkGpout\dCtrlAuxsrc
to: clocks::vals::ClkGpoutCtrlAuxsrc
check: NoCheck
- MergeFieldsets:
from: clocks::regs::ClkGpout\d(Ctrl|Div)
to: clocks::regs::ClkGpout$1
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