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Merge pull request #20 from jjsuwa-sys3175/Try2AvoidUsingL32R
GCC: Try to avoid using L32R to load 32/64bit constant
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55 changes: 55 additions & 0 deletions
55
patches/gcc10.1/gcc-try-to-avoid-using-L32R-to-load-32-64bit-const.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,55 @@ | ||
| diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c | ||
| index 953f90a0..14be4081 100644 | ||
| --- a/gcc/config/xtensa/xtensa.c | ||
| +++ b/gcc/config/xtensa/xtensa.c | ||
| @@ -1072,6 +1072,21 @@ | ||
|
|
||
| if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16) | ||
| { | ||
| + /* Try to emit MOVI.N + SLLI sequence, that is smaller than L32R + constant pool. */ | ||
| + if (TARGET_DENSITY && mode == SImode && register_operand (dst, mode)) | ||
| + { | ||
| + int srcval = INTVAL (src); | ||
| + int shift; | ||
| + if (! (srcval & 1)) | ||
| + for (srcval >>= 1, shift = 1; ! (srcval & 1) && shift < 32; srcval >>= 1, shift++) | ||
| + if (srcval >= -32 && srcval <= 95) | ||
| + { | ||
| + emit_move_insn (dst, GEN_INT (srcval)); | ||
| + emit_insn (gen_ashlsi3_internal (dst, dst, GEN_INT (shift))); | ||
| + return 1; | ||
| + } | ||
| + } | ||
| + | ||
| src = force_const_mem (SImode, src); | ||
| operands[1] = src; | ||
| } | ||
| diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md | ||
| index 8e304a6f..dbb36b11 100644 | ||
| --- a/gcc/config/xtensa/xtensa.md | ||
| +++ b/gcc/config/xtensa/xtensa.md | ||
| @@ -721,8 +721,22 @@ | ||
| (match_operand:DI 1 "general_operand" ""))] | ||
| "" | ||
| { | ||
| - if (CONSTANT_P (operands[1]) && !TARGET_CONST16) | ||
| - operands[1] = force_const_mem (DImode, operands[1]); | ||
| + if (CONSTANT_P (operands[1])) | ||
| + { | ||
| + /* Split in halves if 64-bit Const-to-Reg moves | ||
| + because of offering further optimization opportunities. */ | ||
| + if (register_operand (operands[0], DImode)) | ||
| + { | ||
| + rtx first, second; | ||
| + split_double (operands[1], &first, &second); | ||
| + emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), first)); | ||
| + emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), second)); | ||
| + DONE; | ||
| + } | ||
| + | ||
| + if (!TARGET_CONST16) | ||
| + operands[1] = force_const_mem (DImode, operands[1]); | ||
| + } | ||
|
|
||
| if (!register_operand (operands[0], DImode) | ||
| && !register_operand (operands[1], DImode)) |
55 changes: 55 additions & 0 deletions
55
patches/gcc10.2/gcc-try-to-avoid-using-L32R-to-load-32-64bit-const.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,55 @@ | ||
| diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c | ||
| index 953f90a0..14be4081 100644 | ||
| --- a/gcc/config/xtensa/xtensa.c | ||
| +++ b/gcc/config/xtensa/xtensa.c | ||
| @@ -1072,6 +1072,21 @@ | ||
|
|
||
| if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16) | ||
| { | ||
| + /* Try to emit MOVI.N + SLLI sequence, that is smaller than L32R + constant pool. */ | ||
| + if (TARGET_DENSITY && mode == SImode && register_operand (dst, mode)) | ||
| + { | ||
| + int srcval = INTVAL (src); | ||
| + int shift; | ||
| + if (! (srcval & 1)) | ||
| + for (srcval >>= 1, shift = 1; ! (srcval & 1) && shift < 32; srcval >>= 1, shift++) | ||
| + if (srcval >= -32 && srcval <= 95) | ||
| + { | ||
| + emit_move_insn (dst, GEN_INT (srcval)); | ||
| + emit_insn (gen_ashlsi3_internal (dst, dst, GEN_INT (shift))); | ||
| + return 1; | ||
| + } | ||
| + } | ||
| + | ||
| src = force_const_mem (SImode, src); | ||
| operands[1] = src; | ||
| } | ||
| diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md | ||
| index 8e304a6f..dbb36b11 100644 | ||
| --- a/gcc/config/xtensa/xtensa.md | ||
| +++ b/gcc/config/xtensa/xtensa.md | ||
| @@ -721,8 +721,22 @@ | ||
| (match_operand:DI 1 "general_operand" ""))] | ||
| "" | ||
| { | ||
| - if (CONSTANT_P (operands[1]) && !TARGET_CONST16) | ||
| - operands[1] = force_const_mem (DImode, operands[1]); | ||
| + if (CONSTANT_P (operands[1])) | ||
| + { | ||
| + /* Split in halves if 64-bit Const-to-Reg moves | ||
| + because of offering further optimization opportunities. */ | ||
| + if (register_operand (operands[0], DImode)) | ||
| + { | ||
| + rtx first, second; | ||
| + split_double (operands[1], &first, &second); | ||
| + emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), first)); | ||
| + emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), second)); | ||
| + DONE; | ||
| + } | ||
| + | ||
| + if (!TARGET_CONST16) | ||
| + operands[1] = force_const_mem (DImode, operands[1]); | ||
| + } | ||
|
|
||
| if (!register_operand (operands[0], DImode) | ||
| && !register_operand (operands[1], DImode)) |