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Merge pull request #21 from jjsuwa-sys3175/improve-shift-ops
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GCC: Improve shift operations
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@earlephilhower
earlephilhower authored Dec 8, 2020
2 parents d753ad6 + 3c90928 commit b604334
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Showing 2 changed files with 150 additions and 0 deletions.
75 changes: 75 additions & 0 deletions patches/gcc10.1/gcc-improve-shift-operations.patch
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Original file line number Diff line number Diff line change
@@ -0,0 +1,75 @@
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 21d60ffa..e82c466d 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -1050,6 +1050,16 @@
operands[1] = xtensa_copy_incoming_a7 (operands[1]);
})

+(define_insn "*ashlsi3_1"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (ashift:SI (match_operand:SI 1 "register_operand" "r")
+ (const_int 1)))]
+ "TARGET_DENSITY"
+ "add.n\t%0, %1, %1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "2")])
+
(define_insn "ashlsi3_internal"
[(set (match_operand:SI 0 "register_operand" "=a,a")
(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
@@ -1062,6 +1072,17 @@
(set_attr "mode" "SI")
(set_attr "length" "3,6")])

+(define_insn "*ashlsi3_3x"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (ashift:SI (match_operand:SI 1 "register_operand" "r")
+ (ashift:SI (match_operand:SI 2 "register_operand" "r")
+ (const_int 3))))]
+ ""
+ "ssa8b\t%2\;sll\t%0, %1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "6")])
+
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=a,a")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
@@ -1074,6 +1095,17 @@
(set_attr "mode" "SI")
(set_attr "length" "3,6")])

+(define_insn "*ashrsi3_3x"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (ashift:SI (match_operand:SI 2 "register_operand" "r")
+ (const_int 3))))]
+ ""
+ "ssa8l\t%2\;sra\t%0, %1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "6")])
+
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=a,a")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
@@ -1093,6 +1125,17 @@
(set_attr "mode" "SI")
(set_attr "length" "3,6")])

+(define_insn "*lshrsi3_3x"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (ashift:SI (match_operand:SI 2 "register_operand" "r")
+ (const_int 3))))]
+ ""
+ "ssa8l\t%2\;srl\t%0, %1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "6")])
+
(define_insn "rotlsi3"
[(set (match_operand:SI 0 "register_operand" "=a,a")
(rotate:SI (match_operand:SI 1 "register_operand" "r,r")
75 changes: 75 additions & 0 deletions patches/gcc10.2/gcc-improve-shift-operations.patch
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Original file line number Diff line number Diff line change
@@ -0,0 +1,75 @@
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 21d60ffa..e82c466d 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -1050,6 +1050,16 @@
operands[1] = xtensa_copy_incoming_a7 (operands[1]);
})

+(define_insn "*ashlsi3_1"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (ashift:SI (match_operand:SI 1 "register_operand" "r")
+ (const_int 1)))]
+ "TARGET_DENSITY"
+ "add.n\t%0, %1, %1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "2")])
+
(define_insn "ashlsi3_internal"
[(set (match_operand:SI 0 "register_operand" "=a,a")
(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
@@ -1062,6 +1072,17 @@
(set_attr "mode" "SI")
(set_attr "length" "3,6")])

+(define_insn "*ashlsi3_3x"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (ashift:SI (match_operand:SI 1 "register_operand" "r")
+ (ashift:SI (match_operand:SI 2 "register_operand" "r")
+ (const_int 3))))]
+ ""
+ "ssa8b\t%2\;sll\t%0, %1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "6")])
+
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=a,a")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
@@ -1074,6 +1095,17 @@
(set_attr "mode" "SI")
(set_attr "length" "3,6")])

+(define_insn "*ashrsi3_3x"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (ashift:SI (match_operand:SI 2 "register_operand" "r")
+ (const_int 3))))]
+ ""
+ "ssa8l\t%2\;sra\t%0, %1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "6")])
+
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=a,a")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
@@ -1093,6 +1125,17 @@
(set_attr "mode" "SI")
(set_attr "length" "3,6")])

+(define_insn "*lshrsi3_3x"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (ashift:SI (match_operand:SI 2 "register_operand" "r")
+ (const_int 3))))]
+ ""
+ "ssa8l\t%2\;srl\t%0, %1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "6")])
+
(define_insn "rotlsi3"
[(set (match_operand:SI 0 "register_operand" "=a,a")
(rotate:SI (match_operand:SI 1 "register_operand" "r,r")

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