Merge pull request #131 from analogdevicesinc/doc-mlhelp

Fix doc in MATLAB help

CI/gen_doc/Makefile

@@ -42,14 +42,14 @@ GITTAG := $(shell git describe --tags HEAD)
 .ONESHELL:
 
 doc_ml:
-	cd ../.. ; \
 	cd docs ; \
 	cp ../../scripts/ports.json . ; \
 	cp ../../scripts/read_ports_json.py . ; \
 	python3 read_ports_json.py ; \
 	MATLAB=ON python3 gen_all_doc.py ; \
 	cd .. ; \
 	mkdocs build -d doc
+	mv doc ../../
 
 doc:
 	cd docs ; \

CI/gen_doc/docs/_pages/targeting.md

@@ -1,4 +1,4 @@
-
+{% include 'header.tmpl' %}
 # HDL Targeting with HDL-Coder
 
 High-Speed Converter Toolbox supports the IP Core generation flow from MathWorks which allows for automated integration of DSP into HDL reference designs from Analog Devices. This workflow will take Simulink subsystems, run HDL-Coder to generate source Verilog, and then integrate that into a larger reference design. The figure below is a simplified block diagram of a SoC (Fabric+ARM) device, where specialized IP are inserted into the receive and transmit datapaths. This is supported on specific FPGA families and high-speed based reference designs. This support is based on the Zynq HDL-Coder and support

CI/gen_doc/docs/gen_md_pages.py

@@ -33,6 +33,8 @@ def gen_toc(pages, devices, designs):
 
     template = env.get_template("toc.tmpl")
 
+    pages.remove('index')
+    pages.remove('ad9081')
     output = template.render(pages=pages, devices=devices, designs=designs)
 
     loc = os.path.dirname(__file__)

Jenkinsfile

@@ -15,6 +15,8 @@ stage("Build Toolbox") {
 		withEnv(['HDLBRANCH='+branchName]) {
 		    checkout scm
 	            sh 'git submodule update --init'
+		    sh 'pip3 install -r ./CI/gen_doc/requirements_doc.txt'
+		    sh 'make -C ./CI/gen_doc doc_ml'
 		    sh 'make -C ./CI/scripts build'
 		    sh 'make -C ./CI/scripts gen_tlbx'
 		}