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cope with I$ miss on teensy #405

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Commits on Oct 3, 2024

  1. cope with I$ miss on teensy

    if the instruction cache is completely flushed *even before* the counter
    is read, under specific situations (presumably when relevant parts of
    show() are on different cache lines), the first bit would not be sent
    (but discarded), often leading to a change in colour.
    
    prevent compiler optimisation across counter reads,
    order the delays so that they are easier to reason about.
    Volker Eckert committed Oct 3, 2024
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