Lab3 update

lab3/db/cmpr_5cc.tdf

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+--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_WIDTH=1 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_5cc
+( 
+	aeb	:	output;
+	dataa[0..0]	:	input;
+	datab[0..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[1..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = (data_wire[0..0] $ data_wire[1..1]);
+	data_wire[] = ( datab[0..0], dataa[0..0]);
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE

lab3/db/cmpr_8cc.tdf

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+--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_WIDTH=4 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_8cc
+( 
+	aeb	:	output;
+	dataa[3..0]	:	input;
+	datab[3..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[9..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
+	data_wire[] = ( datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], ((data_wire[6..6] $ data_wire[7..7]) # (data_wire[8..8] $ data_wire[9..9])), ((data_wire[2..2] $ data_wire[3..3]) # (data_wire[4..4] $ data_wire[5..5])));
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE

lab3/db/cmpr_acc.tdf

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+--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_WIDTH=6 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_acc
+( 
+	aeb	:	output;
+	dataa[5..0]	:	input;
+	datab[5..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[14..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = ((data_wire[0..0] # data_wire[1..1]) # data_wire[2..2]);
+	data_wire[] = ( datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], ((data_wire[11..11] $ data_wire[12..12]) # (data_wire[13..13] $ data_wire[14..14])), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), ((data_wire[3..3] $ data_wire[4..4]) # (data_wire[5..5] $ data_wire[6..6])));
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE

lab3/db/cntr_02j.tdf

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+--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" lpm_modulus=128 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=7 clk_en clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_lpm_counter 2013:04:24:18:08:47:SJ cbx_lpm_decode 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneii_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION cycloneii_lcell_ff (aclr, clk, datain, ena, sclr, sdata, sload)
+WITH ( x_on_violation)
+RETURNS ( regout);
+
+--synthesis_resources = lut 7 reg 7 
+SUBDESIGN cntr_02j
+( 
+	clk_en	:	input;
+	clock	:	input;
+	q[6..0]	:	output;
+	sclr	:	input;
+) 
+VARIABLE 
+	counter_comb_bita0 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita1 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita2 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita3 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita4 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita5 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita6 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_reg_bit1a[6..0] : cycloneii_lcell_ff;
+	aclr_actual	: WIRE;
+	cnt_en	: NODE;
+	data[6..0]	: NODE;
+	external_cin	: WIRE;
+	s_val[6..0]	: WIRE;
+	safe_q[6..0]	: WIRE;
+	sload	: NODE;
+	sset	: NODE;
+	updown_dir	: WIRE;
+
+BEGIN 
+	counter_comb_bita[6..0].cin = ( counter_comb_bita[5..0].cout, external_cin);
+	counter_comb_bita[6..0].dataa = ( counter_reg_bit1a[6..0].regout);
+	counter_comb_bita[6..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir);
+	counter_comb_bita[6..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1");
+	counter_reg_bit1a[].aclr = aclr_actual;
+	counter_reg_bit1a[].clk = clock;
+	counter_reg_bit1a[].datain = ( counter_comb_bita[6..0].combout);
+	counter_reg_bit1a[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
+	counter_reg_bit1a[].sdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[])));
+	counter_reg_bit1a[].sload = ((sclr # sset) # sload);
+	aclr_actual = B"0";
+	cnt_en = VCC;
+	data[] = GND;
+	external_cin = B"1";
+	q[] = safe_q[];
+	s_val[] = B"1111111";
+	safe_q[] = counter_reg_bit1a[].regout;
+	sload = GND;
+	sset = GND;
+	updown_dir = B"1";
+END;
+--VALID FILE

lab3/db/cntr_2ci.tdf

@@ -0,0 +1,115 @@
+--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" lpm_modulus=46 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=6 clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_lpm_counter 2013:04:24:18:08:47:SJ cbx_lpm_decode 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneii_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION cycloneii_lcell_ff (aclr, clk, datain, ena, sclr, sdata, sload)
+WITH ( x_on_violation)
+RETURNS ( regout);
+FUNCTION cmpr_acc (dataa[5..0], datab[5..0])
+RETURNS ( aeb);
+
+--synthesis_resources = lut 6 reg 6 
+SUBDESIGN cntr_2ci
+( 
+	clock	:	input;
+	q[5..0]	:	output;
+	sclr	:	input;
+) 
+VARIABLE 
+	counter_comb_bita0 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita1 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita2 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita3 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita4 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita5 : cycloneii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_reg_bit1a[5..0] : cycloneii_lcell_ff;
+	cmpr2 : cmpr_acc;
+	aclr_actual	: WIRE;
+	clk_en	: NODE;
+	cnt_en	: NODE;
+	compare_result	: WIRE;
+	cout_actual	: WIRE;
+	data[5..0]	: NODE;
+	external_cin	: WIRE;
+	modulus_bus[5..0]	: WIRE;
+	modulus_trigger	: WIRE;
+	s_val[5..0]	: WIRE;
+	safe_q[5..0]	: WIRE;
+	sload	: NODE;
+	sset	: NODE;
+	time_to_clear	: WIRE;
+	updown_dir	: WIRE;
+
+BEGIN 
+	counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin);
+	counter_comb_bita[5..0].dataa = ( counter_reg_bit1a[5..0].regout);
+	counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir);
+	counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1");
+	counter_reg_bit1a[].aclr = aclr_actual;
+	counter_reg_bit1a[].clk = clock;
+	counter_reg_bit1a[].datain = ( counter_comb_bita[5..0].combout);
+	counter_reg_bit1a[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
+	counter_reg_bit1a[].sdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir))))));
+	counter_reg_bit1a[].sload = (((sclr # sset) # sload) # modulus_trigger);
+	cmpr2.dataa[] = safe_q[];
+	cmpr2.datab[] = modulus_bus[];
+	aclr_actual = B"0";
+	clk_en = VCC;
+	cnt_en = VCC;
+	compare_result = cmpr2.aeb;
+	cout_actual = (counter_comb_bita[5].cout # (time_to_clear & updown_dir));
+	data[] = GND;
+	external_cin = B"1";
+	modulus_bus[] = B"101101";
+	modulus_trigger = cout_actual;
+	q[] = safe_q[];
+	s_val[] = B"111111";
+	safe_q[] = counter_reg_bit1a[].regout;
+	sload = GND;
+	sset = GND;
+	time_to_clear = compare_result;
+	updown_dir = B"1";
+END;
+--VALID FILE