allow use modelsim predefined external libs

vunit/project.py

@@ -83,28 +83,37 @@ def add_builtin_library(self, logical_name):
     def add_library(
         self,
         logical_name,
-        directory: Union[str, Path],
+        directory: Union[str, Path, None] = None,
         vhdl_standard: VHDLStandard = VHDL.STD_2008,
         is_external=False,
     ):
         """
         Add library to project with logical_name located or to be located in directory
         is_external -- Library is assumed to a black-box
+
+        :param directory: The path to the external library directory
+                                if None - supposes simulator provides library_name
         """
         self._validate_new_library_name(logical_name)
 
-        dpath = Path(directory)
-        dstr = str(directory)
+        if directory :
+            dpath = Path(directory)
+            dstr = str(directory)
+
+            if is_external:
+                if not dpath.exists():
+                    raise ValueError(f"External library {dstr!r} does not exist")
 
-        if is_external:
-            if not dpath.exists():
-                raise ValueError(f"External library {dstr!r} does not exist")
+                if not dpath.is_dir():
+                    raise ValueError(f"External library must be a directory. Got {dstr!r}")
 
-            if not dpath.is_dir():
-                raise ValueError(f"External library must be a directory. Got {dstr!r}")
+            LOGGER.debug("Adding library %s with path %s", logical_name, dstr)
+        else:
+            dstr = None
+            is_external = True
+            LOGGER.debug("Use library %s", logical_name)
 
         library = Library(logical_name, dstr, vhdl_standard, is_external=is_external)
-        LOGGER.debug("Adding library %s with path %s", logical_name, dstr)
 
         self._libraries[logical_name] = library
         self._lower_library_names_dict[logical_name.lower()] = library.name

vunit/sim_if/modelsim.py

@@ -202,6 +202,15 @@ def create_library(self, library_name, path, mapped_libraries=None):
         """
         mapped_libraries = mapped_libraries if mapped_libraries is not None else {}
 
+        if library_name in mapped_libraries:
+            if mapped_libraries[library_name] == path:
+                return
+            if path is None:  # use existing map
+                return
+
+        if path is None:
+            raise ValueError(f"External library {library_name!r} does not exist")
+
         apath = str(Path(path).parent.resolve())
 
         if not file_exists(apath):
@@ -211,9 +220,6 @@ def create_library(self, library_name, path, mapped_libraries=None):
             proc = Process([str(Path(self._prefix) / "vlib"), "-unix", path], env=self.get_env())
             proc.consume_output(callback=None)
 
-        if library_name in mapped_libraries and mapped_libraries[library_name] == path:
-            return
-
         cfg = parse_modelsimini(self._sim_cfg_file_name)
         cfg.set("Library", library_name, path)
         write_modelsimini(cfg, self._sim_cfg_file_name)

vunit/ui/__init__.py

@@ -207,12 +207,13 @@ def _which_vhdl_standard(self, vhdl_standard: Optional[str]) -> VHDLStandard:
 
         return VHDL.standard(vhdl_standard)
 
-    def add_external_library(self, library_name, path: Union[str, Path], vhdl_standard: Optional[str] = None):
+    def add_external_library(self, library_name, path: Union[str, Path] = None, vhdl_standard: Optional[str] = None):
         """
         Add an externally compiled library as a black-box
 
         :param library_name: The name of the external library
         :param path: The path to the external library directory
+                              if None - supposes simulator provides library_name
         :param vhdl_standard: The VHDL standard used to compile files,
                               if None the VUNIT_VHDL_STANDARD environment variable is used
         :returns: The created :class:`.Library` object
@@ -225,9 +226,12 @@ def add_external_library(self, library_name, path: Union[str, Path], vhdl_standa
 
         """
 
+        if path:
+            path = Path(path).resolve()
+
         self._project.add_library(
             library_name,
-            Path(path).resolve(),
+            path,
             self._which_vhdl_standard(vhdl_standard),
             is_external=True,
         )