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187 Open 429 Closed
187 Open 429 Closed
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Issues list

[Bug] Riviera-PRO component binding not working between libraries
#1073 opened Nov 20, 2024 by SzymonHitachi
[Feature] Open a beta and/or alpha channel
#1072 opened Nov 11, 2024 by nselvara
1
[Bug] Multiline comment containing semicolon : over port declaration breaks vhdl_parser.parse()
#1069 opened Oct 22, 2024 by SzymonHitachi
2
[Bug] Package parsing misses dependencies when use clause is not used
#1068 opened Oct 22, 2024 by SzymonHitachi
1
ghdl Coverage : unknown command option '-fprofile-arcs'
#1066 opened Oct 8, 2024 by Electronics4ever
VCS Mixed Simulation VCS VHDL Verilog Mixed language simulation with UVM
#1065 opened Oct 7, 2024 by kashifminhas
[Bug] check_equal and check_true raises error for values other than '0' and '1'
#1061 opened Sep 25, 2024 by nselvara
3
Check code quality in a continuous way
#1059 opened Sep 20, 2024 by racodond
3
Doesn't work with the GHDL Snap package
#1058 opened Sep 15, 2024 by interfect
1
[FEATURE] Print/save commands outputs/logs from (ModelSim/QuestaSim/Questa Base)
#1057 opened Sep 12, 2024 by nselvara
2
Runtime data input from Python to VHDL
#1050 opened Aug 9, 2024 by suryabvsp
1
OSVVM update
#1046 opened Aug 2, 2024 by c-thaler
9
[Feature] Make check_equal a generic procedure Enhancement
#1030 opened Jun 17, 2024 by nselvara
5
Unaligned access to AXI read slave yields incorrect data
#1019 opened May 24, 2024 by ru551n
4
Is there a way to specify minimum cycles between stalls for AXI stream VC?
#1013 opened May 1, 2024 by cjmeyer
1
Question about "blocking" specifically around the bus_master VCI
#1012 opened May 1, 2024 by nathanaelhuffman
1
Indexing order for 3D integer_array_t doesn't make sense
#1011 opened Apr 30, 2024 by bradleyharden
How to specify test case(s) to run after creating a VUnit instance?
#1010 opened Apr 23, 2024 by cjmeyer
2
VUnit testcases fail if the testcase name contains a colon (SystemVerilog)
#1009 opened Apr 17, 2024 by PossenigM
2
VUnit testcases fail if the last character in a testcase name is a whitespace (VHDL) Bug
#1008 opened Apr 17, 2024 by PossenigM
Force stop simulation
#1006 opened Mar 22, 2024 by nselvara
4
Support for CI (reruns) with waveform output CI Enhancement Question Tool: Surfer
#1003 opened Mar 13, 2024 by oscargus
4
Feature Request: real_array_t similar to integer_array_t Builtins Enhancement
#999 opened Mar 11, 2024 by abaebae
3
GHDL wrong path for stimuli
#988 opened Feb 7, 2024 by albydnc
Providing unit test results in Sphinx documentation
#985 opened Jan 13, 2024 by Paebbels
5
ProTip! Exclude everything labeled bug with -label:bug.