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WIP: GBA LOGO 🎆 🥳 🔥 🎉 #213

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WIP: GBA LOGO 🎆 🥳 🔥 🎉 #213

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98c8c56
LCD: Start work on rendering sprites
AlessioC31 Sep 20, 2023
ebf5ee7
ALU: Fix `carry` calculation
AlessioC31 Sep 24, 2023
df73a26
Thumb: Implement `Lsr` alu operation
AlessioC31 Sep 24, 2023
6341f6d
UI: Show by default the gba display
guerinoni Sep 26, 2023
45e0a27
Thumb: Implement LSL
guerinoni Sep 26, 2023
d99f69b
Better name for tests
guerinoni Sep 26, 2023
09c8b4c
ARM: Implement Software Interrupt
guerinoni Sep 26, 2023
cece30e
Arm: Remove condition in `PSRTransfer` variant
guerinoni Sep 26, 2023
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2 changes: 0 additions & 2 deletions emu/src/cpu/arm/instructions.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -100,7 +100,6 @@ pub enum ArmModeInstruction {
rm_operand_register: u32,
},
PSRTransfer {
condition: Condition,
psr_kind: PsrKind,
kind: PsrOpKind,
},
Expand Down Expand Up @@ -659,7 +658,6 @@ impl From<u32> for ArmModeInstruction {
{
// PSR instruction
return PSRTransfer {
condition,
psr_kind: PsrKind::from(op_code.get_bit(22)),
kind: PsrOpKind::from(op_code),
};
Expand Down
6 changes: 1 addition & 5 deletions emu/src/cpu/arm/mode.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -47,11 +47,7 @@ impl std::fmt::Display for ArmModeOpcode {
ArmModeInstruction::MultiplyLong { .. } => {
"FMT: |_Cond__|0_0_0|__code__|S|_RdHi_|_RdLo_|_Rs__|1_0_0_1|_Rm__|"
}
ArmModeInstruction::PSRTransfer {
condition: _,
psr_kind: _,
kind,
} => match kind {
ArmModeInstruction::PSRTransfer { psr_kind: _, kind } => match kind {
crate::cpu::arm::alu_instruction::PsrOpKind::Mrs { .. } => {
"FMT: |_Cond__|0_0_0_1_0|P|0_0_1_1_1_1|_Rd__|0_0_0_0_0_0_0_0_0_0_0_0_0|"
}
Expand Down
26 changes: 9 additions & 17 deletions emu/src/cpu/arm/operations.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -414,7 +414,7 @@ impl Arm7tdmi {

ArithmeticOpResult {
result,
carry: first_op < second_op,
carry: first_op >= second_op,
overflow: different_sign && sign_op2 == sign_r,
sign: result.get_bit(31),
zero: result == 0,
Expand Down Expand Up @@ -472,7 +472,7 @@ impl Arm7tdmi {
}
}

fn mov(&mut self, rd: usize, op2: u32, s: bool) {
pub fn mov(&mut self, rd: usize, op2: u32, s: bool) {
self.registers.set_register_at(rd, op2);

if s {
Expand Down Expand Up @@ -1080,7 +1080,6 @@ mod tests {
assert_eq!(
op_code.instruction,
ArmModeInstruction::PSRTransfer {
condition: Condition::EQ,
psr_kind: PsrKind::Cpsr,
kind: PsrOpKind::Msr {
source_register: 12
Expand Down Expand Up @@ -1154,7 +1153,7 @@ mod tests {
cpu.execute_arm(op_code);
assert!(!cpu.cpsr.sign_flag());
assert!(cpu.cpsr.zero_flag());
assert!(!cpu.cpsr.carry_flag());
assert!(cpu.cpsr.carry_flag());
assert!(!cpu.cpsr.overflow_flag());
}

Expand Down Expand Up @@ -1587,7 +1586,6 @@ mod tests {
assert_eq!(
op_code.instruction,
ArmModeInstruction::PSRTransfer {
condition: Condition::EQ,
psr_kind: PsrKind::Cpsr,
kind: PsrOpKind::Mrs {
destination_register: 12
Expand Down Expand Up @@ -1704,7 +1702,7 @@ mod tests {
cpu.execute_arm(op_code);

assert_eq!(cpu.registers.register_at(1), 5);
assert!(!cpu.cpsr.carry_flag());
assert!(cpu.cpsr.carry_flag());
assert!(!cpu.cpsr.overflow_flag());
assert!(!cpu.cpsr.zero_flag());
assert!(!cpu.cpsr.sign_flag());
Expand All @@ -1716,7 +1714,7 @@ mod tests {
cpu.execute_arm(op_code);

assert_eq!(cpu.registers.register_at(1) as i32, -5);
assert!(cpu.cpsr.carry_flag());
assert!(!cpu.cpsr.carry_flag());
assert!(!cpu.cpsr.overflow_flag());
assert!(cpu.cpsr.sign_flag());
assert!(!cpu.cpsr.zero_flag());
Expand Down Expand Up @@ -1747,7 +1745,7 @@ mod tests {
cpu.execute_arm(op_code);

assert_eq!(cpu.registers.register_at(1), (i32::MIN + 1) as u32);
assert!(cpu.cpsr.carry_flag());
assert!(!cpu.cpsr.carry_flag());
assert!(cpu.cpsr.overflow_flag());
assert!(cpu.cpsr.sign_flag());
assert!(!cpu.cpsr.zero_flag());
Expand Down Expand Up @@ -1953,7 +1951,7 @@ mod tests {
cpu.execute_arm(op_code);

assert_eq!(cpu.registers.register_at(1), 5);
assert!(!cpu.cpsr.carry_flag());
assert!(cpu.cpsr.carry_flag());
assert!(!cpu.cpsr.zero_flag());
assert!(!cpu.cpsr.overflow_flag());
assert!(!cpu.cpsr.sign_flag());
Expand Down Expand Up @@ -2118,7 +2116,7 @@ mod tests {
cpu.execute_arm(op_code);

assert_eq!(cpu.registers.register_at(1), i32::MAX as u32);
assert!(!cpu.cpsr.carry_flag());
assert!(cpu.cpsr.carry_flag());
assert!(!cpu.cpsr.zero_flag());
assert!(cpu.cpsr.overflow_flag());
assert!(!cpu.cpsr.sign_flag());
Expand Down Expand Up @@ -2151,7 +2149,7 @@ mod tests {
cpu.execute_arm(op_code);

assert_eq!(cpu.registers.register_at(1), i32::MAX as u32);
assert!(!cpu.cpsr.carry_flag());
assert!(cpu.cpsr.carry_flag());
assert!(!cpu.cpsr.zero_flag());
assert!(cpu.cpsr.overflow_flag());
assert!(!cpu.cpsr.sign_flag());
Expand Down Expand Up @@ -2181,7 +2179,6 @@ mod tests {
assert_eq!(
op_code.instruction,
ArmModeInstruction::PSRTransfer {
condition: Condition::AL,
psr_kind: PsrKind::Cpsr,
kind: PsrOpKind::Mrs {
destination_register: 0
Expand Down Expand Up @@ -2210,7 +2207,6 @@ mod tests {
assert_eq!(
op_code.instruction,
ArmModeInstruction::PSRTransfer {
condition: Condition::AL,
psr_kind: PsrKind::Spsr,
kind: PsrOpKind::Mrs {
destination_register: 0
Expand Down Expand Up @@ -2242,7 +2238,6 @@ mod tests {
assert_eq!(
op_code.instruction,
ArmModeInstruction::PSRTransfer {
condition: Condition::AL,
psr_kind: PsrKind::Cpsr,
kind: PsrOpKind::Msr { source_register: 0 }
}
Expand All @@ -2264,7 +2259,6 @@ mod tests {
assert_eq!(
op_code.instruction,
ArmModeInstruction::PSRTransfer {
condition: Condition::AL,
psr_kind: PsrKind::Spsr,
kind: PsrOpKind::Msr { source_register: 0 }
}
Expand All @@ -2286,7 +2280,6 @@ mod tests {
assert_eq!(
op_code.instruction,
ArmModeInstruction::PSRTransfer {
condition: Condition::AL,
psr_kind: PsrKind::Cpsr,
kind: PsrOpKind::MsrFlg {
operand: AluSecondOperandInfo::Register {
Expand Down Expand Up @@ -2314,7 +2307,6 @@ mod tests {
assert_eq!(
op_code.instruction,
ArmModeInstruction::PSRTransfer {
condition: Condition::AL,
psr_kind: PsrKind::Spsr,
kind: PsrOpKind::MsrFlg {
operand: AluSecondOperandInfo::Register {
Expand Down
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