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cpu/stm32l0,l1: Fix ADC initialization order #21011

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cpu/stm32l0,l1: Fix ADC initialization order #21011

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2f8b23a
cpu/stm32l0: fix ADC initialization order
crasbe Nov 18, 2024
5de25c6
cpu/stm32l1: fix ADC initialization & resolution setting
crasbe Nov 19, 2024
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6 changes: 3 additions & 3 deletions cpu/stm32/periph/adc_l0.c
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Original file line number Diff line number Diff line change
Expand Up @@ -46,13 +46,13 @@
{
if ((ADC1->CR & ADC_CR_ADEN) != 0) {
ADC1->CR |= ADC_CR_ADDIS;
while(ADC1->CR & ADC_CR_ADEN) {} /* Wait for ADC disabled */

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keyword 'while' not followed by a single space
}

if ((ADC1->CR & ADC_CR_ADEN) == 0) {
/* Then, start a calibration */
ADC1->CR |= ADC_CR_ADCAL;
while(ADC1->CR & ADC_CR_ADCAL) {} /* Wait for the end of calibration */

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}

/* Clear flag */
Expand All @@ -70,7 +70,7 @@
/* Disable ADC */
if ((ADC1->CR & ADC_CR_ADEN) != 0) {
ADC1->CR |= ADC_CR_ADDIS;
while(ADC1->CR & ADC_CR_ADEN) {} /* Wait for ADC disabled */

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/* Disable Voltage regulator */
ADC1->CR = 0;
ADC1->ISR = 0;
Expand Down Expand Up @@ -128,9 +128,6 @@
/* lock and power on the ADC device */
prep();

/* Enable ADC */
_enable_adc();

/* Reactivate VREFINT and temperature sensor if necessary */
if (adc_config[line].chan == 17) {
ADC->CCR |= ADC_CCR_VREFEN;
Expand All @@ -145,6 +142,9 @@
ADC1->CFGR1 |= res & ADC_CFGR1_RES;
ADC1->CHSELR = (1 << adc_config[line].chan);

/* Enable ADC */
_enable_adc();

/* clear flag */
ADC1->ISR |= ADC_ISR_EOC;

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16 changes: 12 additions & 4 deletions cpu/stm32/periph/adc_l1.c
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Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,7 @@

/* configure the pin */
if ((adc_config[line].pin != GPIO_UNDEF))
gpio_init_analog(adc_config[line].pin);

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full block {} expected in the control structure

/* set ADC clock prescaler */
ADC->CCR &= ~ADC_CCR_ADCPRE;
Expand Down Expand Up @@ -131,8 +131,6 @@
ADC->CCR |= ADC_CCR_TSVREFE;
}

/* enable the ADC module */
ADC1->CR2 = ADC_CR2_ADON;
/* turn off during idle phase*/
ADC1->CR1 = ADC_CR1_PDI;

Expand All @@ -157,12 +155,18 @@
/* lock and power on the ADC device */
prep();

/* set resolution, conversion channel and single read */
/* mask and set resolution, conversion channel and single read */
ADC1->CR1 &= ~ADC_CR1_RES_Msk;
ADC1->CR1 |= res & ADC_CR1_RES;
ADC1->SQR1 &= ~ADC_SQR1_L;
ADC1->SQR5 = adc_config[line].chan;

/* wait for regulat channel to be ready*/
/* only set ADON when ADONS bit is cleared (ADC not ready) */
if(!(ADC1->SR & ADC_SR_ADONS_Msk)) {

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ADC1->CR2 |= ADC_CR2_ADON;
}

/* wait for regular channel to be ready*/
while (!(ADC1->SR & ADC_SR_RCNR)) {}
/* start conversion and wait for results */
ADC1->CR2 |= ADC_CR2_SWSTART;
Expand All @@ -171,6 +175,10 @@
sample = (int)ADC1->DR;
ADC1 -> SR &= ~ADC_SR_STRT;

/* wait for ADC to become ready before disabling it */
while (!(ADC1->SR & ADC_SR_ADONS)) {}
ADC1->CR2 &= ~ADC_CR2_ADON_Msk;

/* power off and unlock device again */
done();

Expand Down
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